Daisy Chaining two AD1938 codecs - ALSA System on Chip driver

Hello Henrix,

I do not have experience using ALSA, but I do see by the two instructions you pasted in that there is a different stream name (I think that is the proper term), for the two parts. ad193x_0 and ad193x_1. Somewhere these will be defined and tied to two different chip select output pins. These chip selects will go to the CLATCH pins on the each individual codec. So when you "talk" to one of the parts it will engage the proper chip select to activate the SPI port on the correct part.

Your statement: "(512 fs DACs / 256 fs ADCs / single line TDM mode). "

Why are the DACs configured for 512 fs and the ADCs are configured for 256 fs? Are you using a master clock to drive the PLL? The only way I see this would be if you wanted to run the DACs at a different sample rate from the ADCs. Then you would run the ADCs off of the PLL and directly clock the DAC off of the master clock input pin. Then the master clock would need to be running at 512x fs. The PLL input would have to be the ALRCLK and the loop filter values would have to be setup for the LRCLK frequencies.

Now  I am fairly sure the statement you made was referring to the bit clock frequency of 512x for the DACs, which is TDM16 and 256x for the ADCs which is TDM 8. So that would be good.

Now, you will have to make some hardware connections to do this. Send me your schematics. Figure 18 in the datasheet pretty much explains what pins to use for the DACs to be daisy chained.

But, your basic question asking if you configure both the part the same, the answer is yes. don't forget to ground the input pins of the part on the end of the chain.

Dave T

Hello Henrix,

I do not have experience using ALSA, but I do see by the two instructions you pasted in that there is a different stream name (I think that is the proper term), for the two parts. ad193x_0 and ad193x_1. Somewhere these will be defined and tied to two different chip select output pins. These chip selects will go to the CLATCH pins on the each individual codec. So when you "talk" to one of the parts it will engage the proper chip select to activate the SPI port on the correct part.

Your statement: "(512 fs DACs / 256 fs ADCs / single line TDM mode). "

Why are the DACs configured for 512 fs and the ADCs are configured for 256 fs? Are you using a master clock to drive the PLL? The only way I see this would be if you wanted to run the DACs at a different sample rate from the ADCs. Then you would run the ADCs off of the PLL and directly clock the DAC off of the master clock input pin. Then the master clock would need to be running at 512x fs. The PLL input would have to be the ALRCLK and the loop filter values would have to be setup for the LRCLK frequencies.

Now  I am fairly sure the statement you made was referring to the bit clock frequency of 512x for the DACs, which is TDM16 and 256x for the ADCs which is TDM 8. So that would be good.

Now, you will have to make some hardware connections to do this. Send me your schematics. Figure 18 in the datasheet pretty much explains what pins to use for the DACs to be daisy chained.

But, your basic question asking if you configure both the part the same, the answer is yes. don't forget to ground the input pins of the part on the end of the chain.

Dave T