About AD1934 at 192kHz without PLL

From AD1934's datasheet, I understand that I can run this device without the PLL. My case is the following :

- AD1934 is master on the I2S link (the device outputs both the bit clock and the L/R clock)

- Stereo data, bit clock at 64xFs, 16-b data, I2S mode

- Input clock : 12.288MHz

- Frame rate : 192000kHz

Here is how the AD1934 is programmed :

PLL and Clock Control 0 : 0x99 

PLL and Clock Control 1 : 0x03 

DAC Control 0 : 0x04

DAC Control 1 : 0x30

DAC Control 2 : 0x18

The result is that the Frame rate is 96kHz instead of 192k...The bit clock runs at 6.144MHz. 

BR,

Igor

PS : A block diagram showing the entire clock tree would help a lot in complement of the description text.

  • 0
    •  Analog Employees 
    on Oct 25, 2016 12:28 AM over 4 years ago

    Hello Igor,

    When you run the part in the direct clocking mode, bypassing the PLL, you must feed it with a master clock that is 512x fs. The 512x fs calculation is done when the fs is set to 48kHz. You have it set to the default which is 256 x fs so you are running at half the rate. You will need to feed it 24.576MHz or turn on the PLL.

    You will have to set the PLL and Clock Control Register 0 bits 2:1 to "10" to get the 512 x MCLK setting.

    Thanks,

    Dave T

  • Thank you Dave, 

    When AD1934 is configured this way :

    - Master on the I2S link (bits 5:4 in DAC control 1 are set),

    - Direct clocking from the MCLKI pin (PLL Off)  (bit 0 of PLL and clock Control 0 is cleared + bits (1:0) of the PLL and clock control 1 are both set)

    - stereo, 16-bit (but this may not be as important)

    Could you give the output frame frequency as a function of :

    - bits(2:1) in PLL and clock Control 0, and 

    -bits (2:1) in DAC control 0 ?

    On my board, it seems that with 12.288MHz clock, INPUT256 set in reg 0, and 48kHz sample rate in reg 2, I get a 24kHz output frequency. I need to program 96kHz in dac control 0 to get 48kHz at the output. By the way, is there any preferred programming sequence of these registers ?

    BR,

    Igor

  • 0
    •  Analog Employees 
    on Oct 25, 2016 8:01 PM over 4 years ago

    Hello Luka,

    This is because the 12.288MHz is the wrong frequency to input into the MCLKI. It is half the rate it needs to be so therefore your output frequencies are half. You have to use a 24.576 MHZ crystal. Sorry I was not clear enough. The setting I mentioned for 512 x fs is for when you use the PLL.

    Dave T

  • 0
    •  Analog Employees 
    on Oct 26, 2016 8:08 PM over 4 years ago

    Hello Luka,

    I did a little investigation and found that there is something missing in the datasheet that is in others from this family of parts. To run the part at 192kHz the part requires a higher frequency that the PLL produces. So you cannot direct clock the part and run at 192kHz fs. You must use the PLL. The fastest you can run in the direct clock mode is 96kHz. Sorry for the late flash of insight.

    Dave T