I'm just trying to get the Audio Codec ADAU1761 to work on the ZedBoard.
The FPGA will provide a 12.288 MHz MCLK and will transmit the audio data via I2S (I2S Mode, 48kHz) to the ADAU1761 (in I2S Slave mode). The ADAU should route the audio data from I2S input to the LineOut outputs of the ADAU1761, without using the DSP.
Therefore I configured the registers, that don't have the default values, in this sequence (via I2C).
- 0x4000, 0x01- 0x401C, 0x21- 0x401E, 0x41
- 0x4020, 0x05- 0x4021, 0x11
- 0x4025, 0xFE- 0x4026, 0xFE
- 0x4029, 0x03- 0x402A, 0x03- 0x40F2, 0x01- 0x40F3, 0x01- 0x40F9, 0x7F- 0x40FA, 0x03
And I don't hear and measure any audio data on the LOUTP/N outputs !?!??!
The I2S interface signals are looking good on the scope and the read back register values are also as expected.
Therefore I guess a bug in my register configuration, but I don't see it :-(
Any help or hints are really appreciated.
Solved, sorry for the posting.
I interpreted the I2S data signal directions wrong, the out signals were driving against each other ... :-(
The software configuration above is working!
Answered and Closed
Hello, I'm a beginner to learn zedboard and I meet too many questions in finding how to provide a 12.288 MHz MCLK from FPGA in order to transmit audio data. I can only find the FCLK in Clock Configuration.Could you please help me?