I'm working with the ADSP-21489 EZ-board, which has an AD1939 clocked on a 12.288 MHz oscillator. My test input is an SPDIF audio stream @ 48kHz. Ultimately I want to work in some proprietary routines that require the sample rate to increase to 4x (i.e. I need the DAC to accept samples at 192kHz).
The talkthru example I'm studying (SPDIFToAnalogTalkthruwithSRC for the ADSP-21489 EZ-board) forwards samples from the SPDIF input (via the ADSP-21489's SPORT3 and SPORT4) to the DAC of the AD1939. It appears to be using the AD1939's ALRCLK as the serial clock.
My trouble is, when I try to change the sample rate in init1939viaSPI.c from 48kHz to 192kHz, the ALRCLK doesn't change, which means the AD1939 is still pulling samples at the old 48kHz rate.
I'm having a hard time understanding the "Clock Signals" section in the AD1939 REV E datasheet. Could someone share some additional insight as to what these paragraphs are trying to say (maybe an example or two that relate to my situation)? =)
Assuming I want to keep the AD1939 clocked on an oscillator (rather than feeding it an external clock), is the only way to get the DAC to read samples at 192kHz to swap the 12.288 oscillator out for a 49.152 MHz oscillator?
I answered my own question. It was something silly - as is usual with code/bugs.
The code I was writing to upsample 48k to 192k was correct, but there was a setting in CCES that was preventing new code from compiling and loading, so my two questions are "overcome by events".
Somehow I had changed the configuration from Debug to Release, which was preventing changes to CCES code from compiled and loaded into the processor. The setting can be changed by going to the project's properties -> C/C++ Build -> Build Variables, and the Manage Configurations button at the top. Active configurations can be set in this dialog box.
After fixing that setting, the code compiled/loaded and now my clock AD1939 signals are scaled as I would expect.