It seems as though the ADC gain is not independent from the DAC gain. Is this correct? And, I guess, if so...why? I am having issues where I cannot even get a 5 mvpp signal input without clipping.
The ADC gain is simple a digital gain that is part of the Sigma-Delta decimator process. It is only for the ADC. It is after the data has been sampled and before it is sent to the serial port. The ADC and the DAC sections are reasonably separated. There are a few little things they share like the PLL output, but otherwise, you can clock them at totally different rates if you like.
I think you are doing something wrong in your hardware. Please send a schematic so I can see what might be happening. My crystal ball is in the shop so I am at a disadvantage. I think I may know what you are doing but I don't want to guess.
I suppose my confusion stems mostly from this perplexing paragraph from the datasheet on page 16:"The internal reference can be disabled in the PLL and ClockControl 1 register, and FILTR can be driven from an externalsource. This configuration can be used to scale the DAC outputto the clipping level of a power amplifier based on its powersupply voltage. The ADC input gain varies by the inverse ratio.The total gain from ADC input to DAC output remainsconstant."
I'm afraid I cannot share schematics as this is a company matter, but I can tell you is is singled ended and buffered. I am testing with direct input from a function generator and the same issue of signals 5 mv or greater persists no matter single ended or differential. But from what I'm hearing from you is that the ADC gain is nothing like a PGA and is just a part of the sigma-delta architecture. How then does it vary, and by what inverse ratio in particular?Thanks,HK
Right now I do not need to see the entire schematic. What I need is the input stage and how it connects to the ADC inputs.
Then I need to see what you are doing with the CM pin and also the FILTR pin.
Just small pieces of the schematic.
The way the ADC and the DACs work is like this: The power into the codec is single ended so for the ADC or the DAC to be able to convert a positive or negative number, the voltage has to swing above or below what is a zero level. If you have bi-polar power then the zero level will be really close to zero volts. But with single ended power it is halfway between ground and power. That is the Common Mode voltage. It is derived from an internal source but can be shut off and driven from an outside DC source.
The FILTR is the reference voltage for the DAC. If you increase or decrease this voltage it will change the full scale level that the DAC is converting to. So this is why the note is in the datasheet. You can slightly adjust the full scale point if needed. Few people do this.
So back to your clipping issue. If your circuit is not cap coupled then it will be pulling down the common mode voltage and so you will be getting a clipped half wave signal that is upside-down. Because the negative swing will be fully clipped and the positive swing will be converted as a negative number. So a signal as small as 5mV will clip the converter. This is what I think is going on but without seeing the schematics I am only guessing.
If you cannot even share small screenshots of your schematics then tell me this in your reply. I will use other methods to contact you.
Dave,Below is an image of my input stage. Please let me know if theres anything that would be a show stopper.Thanks,HK
Also, here are the cm and filtr connections. Filtr has had a 10 uF cap added to it per the datasheet, it just hasn't made it onto the schematic yet.