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AD1854 to AD1852

Hi

My customers chose the AD 1854 as an alternative to the AD 1852, which became an EOL.
The customer buffered the audio output of the AD 1854 and the customer gave control signals and data to the AD 1854 in the same way as the AD 1852.
However, AD 1854 did not behave similarly.
I doubt the MASTER CLOCK AUTODIVIDE FEATURE circuit.
Because the problem seems not to be an audio signal.
We are giving a burst clock to the AD 1854.
The burst clock is accepted by the data sheet, just like the AD 1852.
Is it wrong to give the same control signal to the AD 1854 and AD 1852?

 

Best regards

  • I am glad that my customers are likely to succeed in converting from AD1854 to AD1852.
    Customers and we narrowed down the issue.
    Your little comment will complete the project successfully.
    Please let me know only this part.

    The data sheet of the AD1852 which is a substitute says "In normal operation, there are 64 bit clocks per frame (or 32 per half frame). When the SPI word length control bits (Bit 8 and Bit 9 in the SPI control register) are set to 24 bits (0: 0), the serial port begins to accept data starting at the eighth bit clock pulse after the LRCLK transition.

    (AD1852 Datasheet Rev. A | Page 12 of 20)
    For AD1852, since BCLK = 3.072 MHz when LRCLK = 48 KHz, BCLK = 6.144 MHz is not a normal (= correct) usage method.
    On the other hand, no similar description was found in the data sheet of AD1854 (product of EOL), and it was operating even at BCLK = 6.144 MHz.

     

    We and our customers think like the above, is this correct?

    Best regards

  • Hello Mochi,

    For your earlier post I can say that the SPI control is not the same for both parts so that must be changed.

    So I am making the assumption based on your questions that you are sending right justified serial data to the part correct?  Then you would like to send it a BCLK signal of 6.144MHz?

    Since the BCLK signal only has the purpose of shifting in data into the serial port buffer and then loading it into the DAC as a parallel word at the end of the LRCLK cycle, most of our parts will function fine with a BCLK that is twice the frequency that it should be. It will just shift in faster. However, this all depends on how the part was built. If you are sending it a BCLK that is 6.144MHz and you are not getting proper audio out of the DAC then I would say that it was not designed to account for this situation. The signal it is expecting is a 3.072MHz BCLK with 64 transitions per frame.

    It all depends on how the data is transferred and how the digital section was designed. I do not have access to the design files or to the designer. Is it possible to lower the BCLK frequency to at least test that all the other pins and registers are properly setup?

    Dave T

  • You said "If you are sending it a BCLK that is 6.144 MHz and you are not getting proper out of the DAC then I signal it is not that designed. MHz BCLK with 64 transitions per frame. "
    This is the customer's design intact.
    This design is dedicated to the AD 1852 and well verified by customers.
    This design is working properly.

     

    We were convinced that the format and signal of the design were correct.
    I will report that the customer gave up pursuit of failure and decided to proceed with the newly designed design.

     

    Thank you for your support.
    Thank you very much.