I2S Isolation ADAU1372

Hello,

I am working with the ADAU1372 connected to an fpga evaluation board. I send and receive the data via I2S. Now I face the problem that I see random peaks on the DAC Output. For synchronization MCLK comes from the fpga board with 26 MHz. PLL activated on the ADAU1372 like described in the data sheet and works as master. First I thought the peaks arise out of problems in my IPCore on the fpga, but when I disconnected the GND between the two board the peaks nearly disappeared. I also tried to disconnect the USB power supply and use an external supply. Nevertheless the peaks are there. The fgpa board has a seperate power supply. I also recognized that I need to set the drive strengh to high. I placed no additional resistors in the data signals. With drive strengh on low there was no output on ADC_SDATA0 at all. Is it necessary to place an Isolator between the two boards for a proper functionality?

Best regards

Marc 

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  • 0
    •  Analog Employees 
    on Sep 26, 2017 8:55 PM

    Hello MarcvE,

    Thanks for sending your project. The settings all look good from a quick look at the project.

    This is an interfacing issue. The symptom of it getting better when ground is disconnected is a good sign.

    You need to keep the wires as short as possible.

    You need to run a ground wire along with the BCLK, LRCLK and SDATA lines. This will help.

    You need to start at a low sampling rate, like 48kHz and see how it works. If you are trying to run at 192kHz you will have difficulty. 96kHz you could probably get it to work with careful interfacing but when it comes to fly-wire connections the fast sample rates are a problem. You can get it to work once you have your own hardware with both parts on the same PCB.

    It would be good to have them both on the same power supply but either way, you must ground the two boards together. With bus powered designs this can cause ground loops so in that sense a USB isolator might be a good idea.

    You should be using a series resistor on each clock and data line. I have gotten away with it in the lab but clicks and pops are often heard when doing that. Then cranking up the drive strength can sometimes only make things worse. But putting in a dampening resistor and then increasing the drive strength might work well.

    This is a quick response., I have to go into a meeting. Try some of this and let me know how it goes.

    Dave T

  • Dear Dave,

    thank you very much for your fast feedback. Besides two errors in my fpga IPCore shorter wires and additional ground wires along the data wires solved the emc problems. 

    Best regards

    Marc