I'm going to use this ADAU1966A in my upcoming project for an audio application. We're having 3 different audio bandwidth in our application.
(a) The first type will have 10KHz audio bandwidth with 31.25KHz sampling rate.
(b) The second type will have 2.4KHz audio bandwidth with 7.81KHz sampling rate.
(c) The third type will have 150Hz audio bandwidth with 976Hz sampling rate.
Each type will have 8 Audio output channel. So totally 24 audio output is required for us. Hence we've preferred to use two ADAU1966A for this 24 audio output requirement. The first ADAU1966A will be for audio type (a) & (b) by making the (b) type also with 31.25KHz sampling rate. The second ADAU1966A will be for audio type (c) with 976HZ sampling rate. We're preferred to operate this ADAU1966A in slave, stereo left justified mode with direct MCLK input to the DAC by bypassing the PLL section. We're having a following query to proceed further with the implementation.
1. The sample Rate Select (b00) in DAC Control 0 Register is stating 32/44.1/48KHz. Is it recommended to use any of these three sampling rate values or anything within this range we can use?
2. Can we use below 32KHz sampling rate with this ADAU1966A? Because for audio type (c), the bandwidth itself 150Hz. Hence there is no use of going more than 32KHz sampling rate?
Hello Loganathan N,
As you have read in the datasheet the minimum sample rate is 32kHz but that is when you use the PLL. The PLL will have difficulty locking at frequencies below 32kHz fs. The solution to going even lower is to direct clock the part and bypass the PLL.
You will need to disable the PLL_MUTE function that mutes the audio when the PLL is not locked. It is in the PLL_CLK_CTRL1 register. This register also has the CLK_SEL bit to select the MCLK from the MCLKI pin.
You can also power down the PLL in the BLCOK POWER-DOWN Control 1 register. You will still need to supply the 2.5V to the PLLVDD pin since there are other parts of the chip that uses that power pin.
What you will need to supply the part with are valid MCLK, BCLK and LRCLK signals. The MCLK needs to be 512 x fs. The BCLK will depend on the serial data format so I will not go into that right now.
So your 31.25kHz fs is really close to the minimum limit. This will probably work fine since we have to guard-band our specifications. If your application requires this to function at temperatures then you probably would not want to push this specification below the minimum. If you are operating at room at all times then it will probably be fine. If you run an MCLK of 512 x fs even with the PLL and set the MCS bit properly then I am confident it will work fine at 31.25kHz fs.
Now your question about the sampling rate settings. It is listed in the datasheet as 32/44.1/48kHz. The setting sets up the proper clock dividers but the actual frequency is selected by giving the part a slightly different MCLK input frequency.
So a 12.288MHz clock will produce a 48kHz sampling rate when set to the 256 x fs mode. An 11.2896 MHZ clock will produce a sampling rate of 44.1kHz with the same DAC and PLL settings.