AD1939 DAC outputs

Our system uses SC582 interfaced to multiple AD1939. I cannot generate sinusoidal output on the DAC. I see only square wave output. I know this is very vague, but begin the conversation somewhere, right?

  • 0
    •  Analog Employees 
    on Jul 8, 2020 3:23 PM 28 days ago

    Hello tomleick,

    Yes, this is a place to start... So what is wrong with square waves? they can be very useful for digital electronics! Slight smile So you have found a way to use the part as a clock generator. 

    Gee, there are so many ways this could happen so we have to start to narrow down the possibilities. 

    1) Look at the signals being sent to the codec. 

    So the questions for that is:

    What is the bitclock frequency?

    What is the LRCLK/Frame frequency?

    What is the Master Clock frequency?

    Are you using the PLL?

    Can you take some screenshots of the clocks and data paying attention to the persistence setting on the scope and do not do a single sweep. 

    My post here explains this more:

    https://ez.analog.com/audio/f/discussions/3510/how-to-take-meaningful-screenshots-of-i2s-audio-signals

    Then for the second set of questions would be about the codec settings.

    Can you send me the register settings you are using?

    Then where is the audio coming from? Are you taking the ADC output of the codec and turning it around and sending it to the DAC or are you using an oscillator in the DSP?

    A hardware schematic would also be helpful. There could be issues with the reference voltages. 

    That is a start. 

    Thanks,

    Dave T

  • Really impressed with the immediate response. Thank you so much.

    First, an update: while looking into capturing wave forms and register settings, we were able to write the sharc's data from the codec right back into the codec input and pass the received audio to the DAC output. Sine in sine out. This shows us that one of the processes executing in the sharc was part of our issue. Also we noticed that based on our clock configuration, we used the wrong value components for the loop filter.

    Answers to your questions:

    Bitclock frequency is 8.182MHz

    LRCLK frequency is 32kHz

    MCLK is 12.288MHz

    We are using the PLL.

    Screen shots attached.

    Register settings:

    PLL_CCTL0 = 0b10011011 (ENA_ADC_DAC | PLL_IN_MCLK | MCLK_OUT_OFF | INPUT384 | PLL_PWR_DWN)

    PLL_CCTL1 = 0b00000000 (DIS_VREF | ADC_CLK_PLL | DAC_CLK_PLL)

     

    DAC_CTL0 = 0b00001000 (DAC_FMT_I2S | DAC_BCLK_DLY_0 | DAC_SR_48K | DAC_PWR_UP)

    DAC_CTL1 = 0b01110000 (DAC_BCLK_POL_NORM | DAC_BCLK_SRC_INTERNAL | DAC_BCLK_MASTER | DAC_LRCLK_MASTER | DAC_LRCLK_POL_NORM | DAC_CHANNELS_2 | DAC_LATCH_MID)

    DAC_CTL2 = 0b00000000 (DAC_OUT_POL_NORM | DAC_WIDTH_24 | DAC_DEEMPH_FLAT | DAC_UNMUTE_ALL)

     

    ADC_CTL0 = 0b00000000 (ADC_SR_48K | ADC_R2_UNMUTE | ADC_L2_UNMUTE | ADC_R1_UNMUTE | ADC_L1_UNMUTE | ADC_HP_FILT_OFF | ADC_PWR_UP)

    ADC_CTL1 = 0b01000100 (ADC_LATCH_MID | ADC_FMT_AUX | ADC_BCLK_DLY_0 | ADC_WIDTH_24)

    ADC_CTL2 = 0b11101000 (ADC_BCLK_SRC_INTERNAL | ADC_BCLK_MASTER | ADC_CHANNELS_8 | ADC_LRCLK_MASTER | ADC_LRCLK_POL_NORM | ADC_BCLK_POL_NORM | ADC_LRCLK_FMT_50_50) // Generates No signal.

    //ADC_CTL2 = 0b11101000 (ADC_BCLK_SRC_INTERNAL | ADC_BCLK_MASTER | ADC_CHANNELS_8 | ADC_LRCLK_MASTER | ADC_LRCLK_POL_NORM | ADC_BCLK_POL_NORM | ADC_LRCLK_FMT_PULSE) // Generates Square wave with correct frequency.

     

    PLL_CCTL0 = 0b10011011 (ENA_ADC_DAC | PLL_IN_MCLK | MCLK_OUT_OFF | INPUT384 | PLL_PWR_UP)

    //Read PLL_CCTL1 Register until PLL indicates lock (PLL_CCTL1 & AD1938_PLL_LOCK) != AD1938_PLL_LOCK

    Audio from signal generator to CODEC ADC (input op amp) sent to Sharc, direct write back to CODEC DAC.

    I will take applicable excerpts from the schematic and attach. 

    Thanks again!

    AD1939_scopecapture.zip

  • 0
    •  Analog Employees 
    on Jul 13, 2020 7:17 PM 23 days ago in reply to tomleick

    Hello tomleick,

    Thanks for the info. Sorry for the delay. Things have been rather busy. 

    At first I thought I saw an issue with the bitclock frequency but I think it is just a measurement. 8.182MHz does not divide evenly by 32K but I think it is a round off error from the measurements. Once I saw your register settings I see that the clocks of the DSP are the masters so it will be the correct ratio. 

    Most of your settings look good. I see you are using TDM8 for the ADC output and I2S for the DAC inputs. This is all fine, the part is capable of doing this. 

    One thing that did pop out at me it this:

    ADC_CTL1 = 0b01000100 (ADC_LATCH_MID | ADC_FMT_AUX | ADC_BCLK_DLY_0 | ADC_WIDTH_24)

    You have the data format as the AUX mode. You need to change this to TDM mode. AUX mode will use the DAC clocks and they are different. IT also changed some of the functions of the DAC pins. See table 12 in the datasheet for details. Unless you are using external DACs and ADCs you should not be using this mode. 

    Good find with the loop filter components. They are important and PCB layout is also important. Since you have the PLL locking then you are most likely OK. 

    Dave T