ADAU1361 I2S Startup BCLK / LRCLK synchronization


We are currently trying to improve our system which is mainly based on the ADAU1361 for all the clocking purpose (our Blackfin DSP is connected to the ADAU I2S. The DSP SPORT is set as  slave, so that it is clocked using the ADAU BCLK/LRCLK).

The problem we have at the moment is that the I2S signals at ADAU startup are not consistent. Sometimes, the startup is "correct" (i.e : there's 32bits for the left channel, 32bits for the right channel), sometimes, the first frame starts with only a few bits for the left channel. See captured signals at the end of the message.

The question is wether it is possible to 'reset' the I2S port so that it always starts correctly (i.e 32bits for the left channel) ?

During power down of the ADAU, we set the Serial Port Control register to be SLAVE, and we set it back to master only after the correct configuration has been set (PLL, wait for lock, configuration of various registers, fs, ...).

Regards, Jerome

Correct Startup :

Incorrect startup:

  • 0
    •  Analog Employees 
    on Jun 9, 2020 6:51 PM 1 month ago

    Hello Jerome,

    This is an excellent question and I thought about it for a while but I do not think there is a solution internal to the part. The clocks are divided down from the master clock so they are simply that, dividers/counters. Then the control of the direction of the clocks, master/slave, comes from the register section of the part. This is simply an enable line. So when the comms port receives the data and shifts it into the destination address, it is asynchronous to anything that is happening inside the part and certainly with the dividers. These clocks are always running and all the register does is enable them to appear at the pin. So this can happen at any point in the audio frame.

    There is the Core Clock Enable at address 0x4000. That would start the internal counters all at one time but they may not be reset to a known position after powerup. Then you cannot write to the entire register set until this core clock is enabled so I do not see that as an option for you. 

    Since you are asking about this I am assuming it is causing a problem for other parts in the system? 

    The only solution I can see would be an external gate to mute the signals until an external logic line goes high and that would need to be timed with the start of a frame. 

    Dave T

  • Hi,

    Thanks for your detailed answer.

    This 'behavior' is not really problematic for the *real* functionnality of the product (I mean that the Blackfin SPORT which is on the other end of the I2S bus seems to be ready to handle such cases) but we expected to be able to use these signals to 'timestamp' the ADAU startup (the 96Khz which is generated by the ADAU is an important clock in our system, as we can't rely on the real-time from linux).. Anyway, we found a solution using a busy loop on the frame clock of the ADAU to timestamp its startup, along with the Blackfin SPORT registers.

    Regards, Jerome