I'm using the codec ad1934 to have 2 channels with I2S protocol but I can't find several informations in the datasheet. I'm using a 16,934 mHz crystal oscillator for the mclk but it doesn't run. All the register values are at 0x00.  What should be the value of bypass capacitor of the quartz? How can I adapt the quartz if an other sample frequency is needed? Can you help me to solve this issue? Thank you a lot.

  • 0
    •  Analog Employees 
    on Apr 13, 2020 8:56 AM 10 months ago


    Moved your query to Audio community.



  • 0
    •  Analog Employees 
    on Apr 13, 2020 7:46 PM 10 months ago

    Thank you Ivan for moving the post.

    Hello isantos,

    First thing is to get the PLL to lock. If you are reading all registers as zeros then the PLL is not locked. 

    The frequency of 16.934MHz is too high for the PLL in the default 256 x fs mode. The max is stated in table 7 which is 13.8MHz. 

    So you must at least change to 512 x fs mode, or maybe 384 x fs mode. This means that your sampling rate will be multiples of ~33.074kHz which is a strange rate. The oscillator frequency does not divide evenly by 256 or 512. In 384 x fs mode the sampling rate will be 44.09895833 which is almost 44.1kHz. So perhaps this is what you are going for?

    PLL Clock and Control Register 0 has bits 2:1 for setting the PLL divider rate. 

    The other thing you need to do in this same register is to turn on the internal master clock. Bit 7 must be = 1 for the part to function. The default is zero so since you said you read all registers at zero this is part of your problem. ( I have forgotten to set this in the lab as well and wondered why the part was not working. ) 

    Regarding the crystal bypass cap values, you can consult the crystal manufacturer for recommendations. This part has an input capacitance of 5pf so that should help with the calculations.

    PLL Clock Control Register 1 bit 3 is the PLL lock bit. Read it to see if it is "1", then the PLL is locked. 

    Dave T