Products Mentioned

ADAU1761 Production
The ADAU1761 is a low power, stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record and playback at 14 mW from...
Datasheet
ADAU1761 on Analog.com

Thread Details

  • State Verified Answer
  • Replies 7 replies
  • Subscribers 48 subscribers
  • Views 1742 views
  • Users 0 members are here
Options 

        

            Post
             Go back to editing
        

    

    


    

    









		


















	
	
			
	
			
		
	
	
		

	    
	    
	    		
No audio through ADAU1761

		
	
				

			

									
					    mrecoskie
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Apr 6, 2020 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
		    			
    
			    
    Hi,
    

    We have wired together a CP2615 (USB/I2S bridge) and ADAU1761 codec and I am trying to get audio communication.  I was wondering if someone can point out any incompatibility with this combination.  
    

    Below I have attached a snippet of the I2S communication.  It is only transmitting over SDOUT at the moment.  It is set up using a 12 Mhz MCLK and the ADAU1761 is set as slave.  No audio is present.  Probes to eliminate a hardware issue have been taken where possible.
    

     
    

    

    Our register settings for the ADAU1761 are below where 0x70 is the I2C slave address.  The first two bytes after that are the register address - for example 0x40EB followed by the register setting(s) (eg. 0x7F) for that location.  All I2C messages are transmitted and acknowlegded by the chip.  
    

    

    write(0x70, [0x40, 0xEB, 0x7F])
    

    write(0x70, [0x40, 0xF6, 0X00])
    

    write(0x70, [0x40, 0x00, 0x0F])
    

    write(0x70, [0x40, 0x02, 0x00, 0x7D, 0x00, 0x0C, 0x21, 0x01])
    

    delay_ms(100)
    

    write(0x70, [0x40, 0x15, 0x00, 0x40])
    

    write(0x70, [0x40, 0x11, 0x00, 0x00, 0x00, 0x00])
    

    write(0x70, [0x40, 0x08, 0x00])
    

    write(0x70, [0x40, 0x09, 0x00, 0x01, 0x0F, 0x01, 0x0F, 0x9B, 0x43, 0x00])
    

    write(0x70, [0x40, 0x19, 0x3B, 0x00, 0x00])
    

    write(0x70, [0x40, 0x1C, 0x21, 0x00, 0x41, 0x00, 0x03, 0x09, 0x00, 0x00, 0x00, 0xE6, 0xE6, 0x00, 0x00, 0x03])
    

    write(0x70, [0x40, 0x17, 0x00, 0x00])
    

    write(0x70, [0x40, 0x2A, 0x03, 0x00, 0x00])
    

    write(0x70, [0x40, 0x2D, 0x00])
    

    write(0x70, [0x40, 0x2F, 0x00, 0x00])
    

    write(0x70, [0x40, 0x31, 0x00])
    

    write(0x70, [0x40, 0xF5, 0x01])
    

    write(0x70, [0x40, 0xC0, 0x7F, 0x7D, 0x7F, 0x7F, 0x01])
    

    write(0x70, [0x40, 0xC6, 0x00, 0x00, 0x00, 0x00])
    

    write(0x70, [0x40, 0xE9, 0x10, 0x00])
    

    write(0x70, [0x40, 0xD0, 0x00, 0x00, 0x00, 0x00, 0x00])
    

    write(0x70, [0x40, 0xEB, 0x7F])
    

    write(0x70, [0x40, 0xF2, 0x00])
    

    write(0x70, [0x40, 0xF3, 0x00])
    

    write(0x70, [0x40, 0xF4, 0x00])
    

    write(0x70, [0x40, 0xF7, 0x00])
    

    write(0x70, [0x40, 0xF8, 0x00])
    

    write(0x70, [0x40, 0xF9, 0x7F, 0x03])
    

    delay_ms(5)
    

    write(0x70, [0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xE0, 0x00, 0x00, 0x00, 0xFF, 0x34, 0x00, 0x00, 0x00, 0xFF, 0x2C, 0x00, 0x00, 0x00, 0xFF, 0x54, 0x00, 0x00, 0x00, 0xFF, 0x5C, 0x00, 0x00, 0x00, 0xFF, 0xF5, 0x08, 0x20, 0x00, 0xFF, 0x38, 0x00, 0x00, 0x00])
    

    write(0x70, [0x80, 0x08, 0xFF, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xE8, 0x0C, 0x00, 0x00, 0xFE, 0x30, 0x00, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00])
    

    write(0x70, [0x80, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xE8, 0x07, 0x20, 0x08, 0x00, 0x00, 0x06, 0xA0, 0x00, 0xFF, 0xE0, 0x00, 0xC0, 0x00, 0xFF, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00])
    

    write(0x70, [0x80, 0x18, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xC0, 0x22, 0x00, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xE8, 0x1E, 0x00, 0x00, 0xFF, 0xE8, 0x01, 0x20, 0x00, 0xFF, 0xD8, 0x01, 0x03, 0x00, 0x00, 0x07, 0xC6, 0x00, 0x00, 0xFF, 0x08, 0x00, 0x00, 0x00])
    

    write(0x70, [0x80, 0x20, 0xFF, 0xF4, 0x00, 0x20, 0x00, 0xFF, 0xD8, 0x07, 0x02, 0x00, 0xFD, 0xA5, 0x08, 0x20, 0x00, 0x00, 0x20, 0x00, 0xE2, 0x00, 0xFD, 0xAD, 0x08, 0x20, 0x00, 0x00, 0x38, 0x00, 0xE2, 0x00, 0xFD, 0x25, 0x08, 0x20, 0x00, 0x00, 0x00, 0x00, 0xE2, 0x00])
    

    write(0x70, [0x80, 0x28, 0xFD, 0x2D, 0x08, 0x20, 0x00, 0x00, 0x08, 0x00, 0xE2, 0x00, 0x00, 0x05, 0x08, 0x20, 0x00, 0xFD, 0xB0, 0x00, 0xE2, 0x00, 0x00, 0x0D, 0x08, 0x20, 0x00, 0xFD, 0xB8, 0x00, 0xE2, 0x00, 0x00, 0x60, 0x0B, 0x20, 0x00, 0x00, 0x58, 0x0C, 0x22, 0x00])
    

    write(0x70, [0x80, 0x30, 0x00, 0x48, 0x0B, 0x34, 0x00, 0x00, 0x40, 0x0C, 0x22, 0x00, 0x00, 0x20, 0x08, 0x22, 0x00, 0x00, 0x18, 0x09, 0x22, 0x00, 0x00, 0x10, 0x0A, 0x22, 0x00, 0x00, 0x50, 0x00, 0xE2, 0x00, 0x00, 0x68, 0x00, 0xF2, 0x00, 0x00, 0x90, 0x0B, 0x20, 0x00])
    

    write(0x70, [0x80, 0x38, 0x00, 0x88, 0x0C, 0x22, 0x00, 0x00, 0x78, 0x0B, 0x34, 0x00, 0x00, 0x70, 0x0C, 0x22, 0x00, 0x00, 0x38, 0x08, 0x22, 0x00, 0x00, 0x30, 0x09, 0x22, 0x00, 0x00, 0x28, 0x0A, 0x22, 0x00, 0x00, 0x80, 0x00, 0xE2, 0x00, 0x00, 0x98, 0x00, 0xF2, 0x00])
    

    write(0x70, [0x80, 0x40, 0x00, 0xC0, 0x10, 0x20, 0x00, 0x00, 0xB8, 0x11, 0x22, 0x00, 0x00, 0xA8, 0x10, 0x34, 0x00, 0x00, 0xA0, 0x11, 0x22, 0x00, 0x00, 0x50, 0x0D, 0x22, 0x00, 0x00, 0x48, 0x0E, 0x22, 0x00, 0x00, 0x40, 0x0F, 0x22, 0x00, 0x00, 0xB0, 0x00, 0xE2, 0x00])
    

    write(0x70, [0x80, 0x48, 0x00, 0xC8, 0x00, 0xF2, 0x00, 0x00, 0xF0, 0x10, 0x20, 0x00, 0x00, 0xE8, 0x11, 0x22, 0x00, 0x00, 0xD8, 0x10, 0x34, 0x00, 0x00, 0xD0, 0x11, 0x22, 0x00, 0x00, 0x80, 0x0D, 0x22, 0x00, 0x00, 0x78, 0x0E, 0x22, 0x00, 0x00, 0x70, 0x0F, 0x22, 0x00])
    

    write(0x70, [0x80, 0x50, 0x00, 0xE0, 0x00, 0xE2, 0x00, 0x00, 0xF8, 0x00, 0xF2, 0x00, 0x00, 0xB5, 0x08, 0x20, 0x00, 0xFD, 0x60, 0x00, 0xE2, 0x00, 0x00, 0xE5, 0x08, 0x20, 0x00, 0xFD, 0x68, 0x00, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x30, 0x00, 0x00, 0x00])
    

    write(0x70, [0x80, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00])
    

    delay_ms(5)
    

    write(0x70, [0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x67, 0x35, 0x0F, 0x01, 0x31, 0x96, 0x00, 0x7F, 0x67, 0x35, 0x00])
    

    write(0x70, [0x00, 0x0F, 0xFE, 0xCB, 0x9E, 0x0F, 0x81, 0x2E, 0xCB, 0x00, 0x07, 0x48, 0x76, 0x00, 0x0E, 0x90, 0xEC, 0x00, 0x07, 0x48, 0x76, 0x00, 0xBC, 0x50, 0x46, 0x0F, 0xA6, 0x8D, 0xE1])
    

    delay_ms(5)
    

    write(0x70, [0x40, 0xEB, 0x71])
    

    write(0x70, [0x40, 0xF6, 0x01])
    

    write(0x70, [0x40, 0x36, 0x00])
    

    write(0x70, [0x40, 0x36, 0x03])
    
			
    
			
									
		                             
                        

    
    
                                            
                 Audio Signal Processors
                
                                                    
                 SigmaDSP Audio Processors
                
                                                    
                 adau1761
                
                                
            
    
    
    
		
    

				
				        
        		
    
			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		
    

        
        
        
    
					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

    • 
	
      



	
		
	
	



      
	
      
		
      
							
					
      
		
      
		    
		    		    
			
				
									
							        
			
			
			
      •  Analog Employees  
      •  Super User  
      
            
						
                            
            
            				
            
                on Apr 7, 2020 4:43 PM
            
            
						
			            		
      
		
										0
					
	
      

		
		
      
		
      
                                
                                                            
      
					
      Hello mrecoskie,
      

      I think we need to look more closely at the clocking and the I2S signal.
      

      What is your exact master clock frequency?
      

      Your bit clock is not continuous. 
      

      Look at my post about taking screenshots to see what the I2S waveforms should look like. 
      

      https://ez.analog.com/audio/f/q-a/544131/how-to-take-meaningful-screenshots-of-i2s-audio-signals 
      

      For the I2S to be properly read there needs to be exactly 32 bit clocks for every data slot which means 64 bit clocks per sample period. 
      

      Dave T
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

      • 

	

    • 
	
      



	
		
	
	



      
	
      
		
      
							
					
      
		
      
		    
		    		    
			
				
									
							        
			
			
			
        
            
						
                            
            
            				
            
                on Apr 8, 2020 10:48 AM
            
            
												
						in reply to DaveThib
					
										
			            		
        
		
										0
					
	
        

		
		
        
		
        
                                
                                                            
        
					
        Hi Dave,
        

        

        Thanks for responding!  Agreed.  I believe that clocking may be a problem.  The CP2615 provides a 12 MHz master clock to the ADAU1761.  
        

        

        I am happy to collect more captures.  I have a PC based Saleae logic analyzer at my disposal right now.  I read the link you provided.  Were you specifically looking for the analog representation of the signals and/or a different window/phase?
        

        

        I believe the 24 bit clocks for each data slot is correct.  I have configured the BPF bits in the Serial Port Control 1 Register (0x4016) to 010 (48 bits).  
        

        

        But this does lead into some of my concern about the compatibility between the ADAU1761 and CP2615 - three specific points.
        

        

        #1.   Your observation is correct.  The bit clock is not continuous.  Is this an obstacle for the ADAU1761?
        

        #2.  The CP2615 can only run as master and runs a 3.429MHz bit clock.  It’s been pointed out to me that this is an unusual frequency not easily divisible.  What would be the expected result of this?  lost data?  no audio?
        

        #3.  The CP2615 can only provide 16 bit per channel when running full duplex traffic even through it always provides 24 bit clock cycles per channel.   Figure 58 in the ADAU1761 Datasheet (page 42/43) implies it is possible to run 16 bit per channel however it is not clear how this can be configured.  Is it somehow handle inside the ADAU1761 based on incoming traffic? 
        

        

        Does this make sense and are any of these valid concerns?  Your feedback would be invaluable.  Thank you.
        

        

        Mark
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

        • 

	

      • 
	
        



	
			
		
	



        
	
        
		
        
							
					
        
		
        
		    
		    		    
			
				
									
							        
			
			
			
        •  Analog Employees  
        •  Super User  
        
            
						
                            
            
            				
            
                on Apr 9, 2020 1:59 PM
            
            
												
						in reply to mrecoskie
					
										
			            		
        
		
										0
					
	
        

		
		
        
		
        
                                
                                                            
        
					
        Hello Mark,
        

        

        mrecoskie said:
        specific points.
        

        

        #1.   Your observation is correct.  The bit clock is not continuous.  Is this an obstacle for the ADAU1761?
        

        Yes, it is. 
        

        

        mrecoskie said:
        #2.  The CP2615 can only run as master and runs a 3.429MHz bit clock.  It’s been pointed out to me that this is an unusual frequency not easily divisible.  What would be the expected result of this?  lost data?  no audio?
        

        Where do they get this frequency from? It is not divisible by 12.288MHz, or 12MHz, it is not divisible by 16 or 24. 
        

        No Audio is the result. The DSP will not see this as a valid signal. 
        

        

        mrecoskie said:
        #3.  The CP2615 can only provide 16 bit per channel when running full duplex traffic even through it always provides 24 bit clock cycles per channel.   Figure 58 in the ADAU1761 Datasheet (page 42/43) implies it is possible to run 16 bit per channel however it is not clear how this can be configured.  Is it somehow handle inside the ADAU1761 based on incoming traffic? 
        

        When you left justify the data (or one bitclock delay) there is no need for a setting of 16 or 24 bits. It will clock in the bits into the MSB positions and if there is nothing after the 16th bit it will clock in zeros and the data can be processed as a 24 bit signal. So no need for configuration. Only when you right justify the data is there a need to configure it as 16 or 24 bits. The receiving port needs to know where the sign bit is. (the MSB) 
        

        

        Once of our other codecs that have built in sample rate converters might be able to accept this signal but the non-continuous signal will make it constantly recalculate the sample rate. So perhaps not. So what can interface with this part?
        

        Dave T
        

        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
						
						
				
				
		
		
        
			
		
        
	
        

        

        • 

	

      • 
	
        



	
		
	
	



        
	
        
		
        
							
					
        
		
        
		    
		    		    
			
				
									
							        
			
			
			
          
            
						
                            
            
            				
            
                on Apr 9, 2020 2:46 PM
            
            
												
						in reply to DaveThib
					
										
			            		
          
		
										0
					
	
          

		
		
          
		
          
                                
                                                            
          
					
          Hi Dave,
          

          

          Thanks for the confirmation.  It helps.  By the sounds of it we should find a different chip combination.
          

          

          It’s very interesting where a rate of 3.429Mhz came from.  I wish I knew because it seems peculiar. 
          

          

          Just as a curiosity I disabled the DSP but I still didn’t receive any audio.  
          

          

          Your explanation for 16 bit per channel makes perfect sense.  
          

          

          A codec compatibility list for the CP2615 can be found here - https://www.silabs.com/community/interface/knowledge-base.entry.html/2017/05/15/cp2114_cp2614_cp2615-54ad
          

          Compatibility in these cases must be reliant on internal codec implementation details. 
          

          

          Mark
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

          • 

	

        • 
	
          



	
		
	
	



          
	
          
		
          
							
					
          
		
          
		    
		    		    
			
				
									
							        
			
			
			
            
            
						
                            
            
            				
            
                on Apr 9, 2020 2:48 PM
            
            
												
						in reply to DaveThib
					
										
			            		
            
		
										0
					
	
            

		
		
            
		
            
                                
                                                            
            
					
            Hi Dave,
            

            

            Thanks for the confirmation.  It helps.  By the sounds of it we should find a different chip combination.
            

            

            It’s very interesting where a rate of 3.429Mhz came from.  I wish I knew because it seems peculiar. 
            

            

            As a curiousity I disabled the DSP but I still didn’t receive any audio.  
            

            

            Your explanation for 16 bit per channel makes perfect sense.  
            

            

            A codec compatibility list for the CP2615 is on their forum.  Compatibility in these cases must be reliant on internal codec implementation details. 
            

            

            Mark
            
			
            

		
			
	      

		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
						
				
						
				
				
		
		
            
			
		
            
	
            

            

            • 

	

          • 
	
            



	
		
	
	



            
	
            
		
            
							
					
            
		
            
		    
		    		    
			
				
									
							        
			
			
			
              
            
						
                            
            
            				
            
                on May 31, 2020 2:08 PM
            
            
												
						in reply to mrecoskie
					
										
			            		
              
		
										0
					
	
              

		
		
              
		
              
                                
                                                            
              
					
              Hello,
              

              Just so you know, the 3.429 MHz clock comes from the internall oscillator on the CP2615, which runs at 48MHz

              It is divided by 4 to generate MCLK and by 14 to generate BCLK
              
			
              

		
			
	      

		
		
	
              
	
              
		
              
			
		
              
	
              
	
              
		
						
						
				
						
				
				
		
		
              
			
		
              
	
              

              

              • 

	

            • 
	
              



	
		
	
	



              
	
              
		
              
							
					
              
		
              
		    
		    		    
			
				
									
							        
			
			
			
              •  Analog Employees  
              •  Super User  
              
            
						
                            
            
            				
            
                on Jun 5, 2020 4:21 PM
            
            
												
						in reply to jsilva
					
										
			            		
              
		
										0
					
	
              

		
		
              
		
              
                                
                                                            
              
					
              Hello jsilva,
              

              Thanks for the info. So this is the root of the problem. 48MHz /4 = 250 x 48kHz. So the master clock is 250 times the sample rate. Most audio parts use 256 x fs. 
              

              Then what is interesting is that 48MHz / 14 does not divide evenly. 3428571.428571429 and this is probably cutoff due to the digit limit of my calculator. So this means that the number of bitclocks will not be exactly even all the time for each frame even if you are running at 48kHz fs with the master clock divisor at 250 x fs. 
              

              So anything that looks at the ratio of bit clock to LRCLK will run into this every X frames and unlock. 
              

              Still wonder why they did this?
              

              Dave T
              

              
			
              

		
			
	      

		
		
	
              
	
              
		
              
			
		
              
	
              
	
              
		
						
						
				
						
				
				
		
		
              
			
		
              
	
              

              

              •