my application: a pair of PDM microphone to ADAU7002, which convert PDM to I2S, then to host processor. I saw the group delay is 3.31 LRCLK cycles. Is it steady over time?
Hello Robert,
I spent a lot of time on that datasheet to give as much info as possible. So I put the Min and Max values to make the point that you picked up that the group delay is by design in the digital…