my application: a pair of PDM microphone to ADAU7002, which convert PDM to I2S, then to host processor. I saw the group delay is 3.31 LRCLK cycles. Is it steady over time?
I spent a lot of time on that datasheet to give as much info as possible. So I put the Min and Max values to make the point that you picked up that the group delay is by design in the digital section so there is no variance with temperature or silicon skews etc.
The 7002 is the same but it was not clear in the datasheet. I did not write that datasheet.
So it will be steady.