I plan to use an AD1938 in TDM mode together with a PIC32MX (or PIC32MZ). Receiving data from the ADC's should work, but it does not support generating 8-channel TDM -- it cannot generate a frame sync (LRCLK) as depicted in the AD1938 document.
The PIC can output data in framed SPI mode, with the required 32 bytes of data per frame, but the frame sync will only be a bit wide (or word wide).
My question is: Does AD1938 care where the second (rising) edge occurs in the frame? I would guess it only cares about the falling edge to determine where the frame starts.
Edit: I will NOT use the onboard PLL to derive MCLK from LRCLK.
It will only look for the edge that it is setup to look for. After that the second edge has to be before it is too close to the edge of the frame, and I mean really close. So it is not a problem to have a one word wide word clock. but you will have to set it up to look for the correct edge. If it is setup for 50/50 then the positive setting will be looking for a falling edge if I recall correctly. Then if you change the setting to pulse type of word sync, then it will be looking for the rising edge of the LRCLK when set to positive. The register settings are not very clear sometimes.
What I suggest is that you temporarily setup the Codec ADC section to be a master and look at the waveforms on a scope. Then set the registers for the waveform you need then change it back to slave. In the pulse mode the LRCLK only have to be at least one BitClock period wide, if it is one entire word then it is not a problem.
Can the PIC 32 produce a 12.288MHz bitclock? That is what will be needed for a TDM 8 signal with 32-bit-wide word slots when running at 48kHz fs.
Dave, thanks for the reply. This is good news. When you say 50/50, do you mean "Latch in the mid cycle" setting in "DAC Control Register 1", bit 0?
The PIC has full control of the frame sync polarity. It also has a flexible Ref Clock that can be fine tuned to whatever I need, and act as source for the SPI clock to keep things in sync.
No, it Is not that setting but when I went to the datasheet to look it up for you I recall now that there is one strange thing in the registers in this part. There is a setting called LRCLK format for the ADC for 50/50 verses pulse but there is no such setting for the DAC. If I remember right when you set the serial format to stereo you will get 50/50 but for TDM settings you will get a pulse. I think the designers were thinking that usually the DACs are clock slaves and did not provide that setting? Just speculating but either way the DAC does not care when the transition occurs during the frame as long as it is at least one bit clock cycle after the start of the frame and soon enough before the end to internally pick it up and be ready for the next start of frame edge. ( that is in nano seconds)