ADAU1701 I2S input and analog input question


     i have a question about ADAU1701 audio input.

     Now,i wanna make an audio product of adau1701.when i sending the I2S audio input. and analog audio input.

but i found the I2S without MCLK. The BCLK is 3.072M

     Now I want to keep my sampling rate at 48Khz, and there will be no switching action. 

     1、Can I use BCLK as MCLK input and set my pll_mode to 64fs (48K * 64).

     2、Will my analog input have an impact here?

     3、Whether the sampling rate is 48Khz under PLL mode of 64fs. Or do we need to change the 12.8m crystal oscillator?

Thank you very much if you can help me with this

  • 0
    •  Analog Employees 
    on Dec 16, 2019 6:36 PM

    Hello terryyuan,

    1) Yes, you can use a 3.072MHz bit clock as a master clock as long as you set the PLL Mode to 64x fs. 

    2) No, but the I2S must always be present and it cannot stop even if you are only using the analog ADC input and not the serial port. The clocking of the part, LRCLK, BCLK and Master clock must continue. 

    3) No you would not need the crystal oscillator at all. 

    In this last question, were you asking if the sampling rate changes? 

    Dave T

  • Hi daveThib:

       Thank you for your answer。

       i am only going to use the 48Khz sampling rate right now and it is not going to change,whether it is analog audio input or I2S input.

        What I am confused about is whether my analog audio can get 48Khz sampling rate under the pllmode input of 64fs and external 12.8m oscillator?

        If my analog audio input can reach a sampling rate of 48Khz and my I2S can also input (BCLK acts as MCLK) at 48Khz without MCLK. I don't think the system will have a lot of problems. 

        According to your second point, I have a little question about whether the I2S can not be disconnected under any circumstances. even if i stopped Mclk,Bclk and LRCLK at the same time. this will have an impact on my requirements and the upper level design.


  • 0
    •  Analog Employees 
    on Dec 17, 2019 7:56 PM in reply to terryyuan

    Hello Terryyuan,

    I have tested this before but your questions made me think of different things to check. 

    The internal clocking on this part is very simple so there are not many options for internal clocking. 

    First, your question about PLL mode. The PLL will lock to the incoming frequency and output the required internal frequencies. So it will multiply the incoming frequency to obtain the 49.152kHz internal core clock. It will also produce the required oversampling clocks for the converters and the LRCLK rates of 48, 96 and 192 along with the bit clock frequencies required. So all you have to do is provide the PLL with the proper input, set the PLL dividers properly (the pins) and then it will all function properly. The internal ADC is going to sample at the oversampling rate and then decimate it down to the core sampling rate. 

    Internal clocking verses external clocking. 

    The master clock must be there always for the part to work. If you are only using the internal converters then all you need is the master clock and it needs to be the correct frequency according to the PLL divider setting and the desired sampling rate. 12.288MHz will give you 48kHz fs when the PLL is set to 256 x fs. If you want to run at 44.1kHz then you need a master clock frequency of 11.2896MHz. 

    If the master clock goes away the DSP stops. This will cause audio possible clicks and pops. 

    If you setup the part to accept I2S signals then you need to do the following:

    Set the GPIO pins to the proper setting. 

    Send the bitclock and LRCLK into the part but it must be synchronized with the master clock. They both need to be derived from the same clock. If they are not then the part shuts down and nothing will work, not even the internal converters. The internal clocking will see this invalid state and shut off all the internal clocks.

    You can work out the hardware such that you can switch to a different master clock but you need to allow for the PLL to lock and mute the audio external to the part. Once you are running with an external clock, the part will synchronize the internal converters off of this new master clock.  

    The strange behavior is this. If you are running on a master clock from some source, then turn on the BCLK and LRCLK that is from a different source, the part will stop working. It will see these clocks and see that it is not synchronized with the master clock and shut down all clocks. If you remove either the LRCLK or the BITCLK, then it will start working again. It seems that there is some internal logic that will ignore the signals on either LRCLK or BCLK pins until there are signals on BOTH pins. Then it will count the pulses and see it is not in sync with the master clock and stop.

    So for you,..

    If your I2S signals go away, you will need to switch to some other master clock source that is 3.072MHz.

    If your BCLK can be setup to stay on even when there is no signal input then that will work out fine.

    If you work out a hardware switch to a different MCLK and the I2S BCLK and LRCLK signals start working, you will need to quickly switch to the bit clock for the MCLK source or you will need to prevent either the bitclock or LRCLK from getting to the GPIO pins until you are ready to switch over. This can be done using the register settings if you have a system controller.

    In your case you would want to stop the LRCLK until you are ready to switch over to the I2S master clock (the bit clock) then allow the LRCLK to go to the part.

    I wish we had sample rate converters on this part but we do not.

    Dave T 

  • Hi daveThib:

       Thank you for your answer. i know more about adau1701.

        the problem will solve that  I am  using a 3.072M input to MCKI pin and set the PLL mode to 64* is enough that my ADC can produce 48khz of audio data and i2s can input 48khz of audio data.

        by the way, it is also impossible to stop the input of external MCLK with i2S.I found that input clock of MCKI pin is related to the internal clock.

        thank you very much for your kind answer.


    terry yuan

  • 0
    •  Analog Employees 
    on Dec 18, 2019 4:54 PM in reply to terryyuan

    Hello terry,

    You are correct about the MCLK input. It is related to the internal sampling clock. The output of the PLL is divided down to produce the clocks. So the master clock cannot stop. 

    The problem I was detailing in my last post is that the clock inputs to the I2S inputs must also be derived from the master clock. if they are not then the entire part stops working. 

    I hope your project goes well. 

    Dave T