I am looking for a way to generate LRCLK and BCLK signals in order to connect two I2S slaves.
So far, I have always had some chip capable of operation in master mode; not this time however.
I could imagine using a clock divider to generate BCLK and LRCLK from MCLK, but im wondering if there is a better method.
How is this usually handled ? Is there an IC suited for this task ?
Thanks in advance !
I suggest you use a SigmaDSP to serve as the clock masters and also to route and process the signals between the two parts.
What are these parts that you are using? If they both can only be slaves then I would guess that they are not meant to be in a system together with nothing else.
DaveThib said:I suggest you use a SigmaDSP to serve as the clock masters and also to route and process the signals between the two parts.
I'd love to do that.
As far as I know, SigmaDSP are fixed to one sample rate and can't change that during operation.
This would be required since resampling is not desired in this case.
DaveThib said:What are these parts that you are using?
One is an embedded streaming solution that communicates the current sample rate to the MCU. The other one is an AKM AK4493.
DaveThib said:If they both can only be slaves then I would guess that they are not meant to be in a system together with nothing else.
Some systems I saw using this streaming device, also have an Xmos chip for USB audio. I believe that the XMOS Chip could be the master device.
Thats not something id like to get into; if avoidable.
You will certainly want to use the ADAU1452 or the ADAU1466/67 line of parts since the AKM DAC is 32 bit and these parts can output the data as 32 bit data.
They are very flexible for clocking. There are so many ways to setup the clocking and we tend to gravitate towards solutions that are easy and flexible so that little to no intervention by the MCU is required. This is what makes the built-in ASRCs so handy but I understand you will not be using them.
There are two methods that come to mind, the first is a bit more complicated but the number of MIPS would be known. The second is simpler to implement but if you are pushing the MIPS usage it might cause some issues with possibly running out of instructions during some frames.
First let me start by saying the DAC should be operated as a slave and the streaming device would be the master for the DAC clocks.
Supply master clock to the SigmaDSP from the streaming device and when the sample rate changes you would have to mute the audio and stop the core and the PLL. Relock the PLL and then restart the core. So this is a little complicated but the entire core would be run from the system master clock and so the sample rate will be divided down from this master clock and therefore the number of instructions per frame would be constant.
Run the SigmaDSP from its own crystal for its master clock input. So it would be free-running and not synchronized with the system master clock. This crystal would only be used to run the core and not for the actual sample rate.
The execution of the DSP code would be triggered from the incoming LRCLK from the streaming device. This is the Start Pulse selection register which can be set to the serial input port.
So the input ports would be a slave so you would have to run the streaming device LRCLK and Bit Clock to both the serial input ports and the serial output ports. Only one of each needs to be connected. We can internally sync the rest of the ports from these signals. So this will synchronize the execution of the program to the incoming rate. The detail is that the number of instructions will be the core rate divided by the sample rate. Since the core rate is coming from the crystal there will be a drifting of these two rates. So the number of MIPS in any particular frame will vary slightly with this drift. It should not be a lot so as long as you do not write a program that uses most of the available MIPS you will be fine. We do have some new features that can track the MIPS usage during operation but I have not had time to write up some examples.
In your original post you said the streaming device is only a slave? It does not generate LRCLK and Bit Clock? often streaming devices are slaves to the network clocks or to a wireless format clock like Bluetooth. So I would expect that it wants to be the master. If it only outputs a master clock rate then we can certainly take that clock in and generate the LRCLK and BitCLK and be the master of the system that is slaved to this master clock. So there is still a bit of confusion on my part so I apologize.
The clocking on these Sigma300 and Sigma350 parts are very flexible.