I2S master without a master

Hi !

I am looking for a way to generate LRCLK and BCLK signals in order to connect two I2S slaves.

So far, I have always had some chip capable of operation in master mode; not this time however.

I could imagine using a clock divider to generate BCLK and LRCLK from MCLK, but im wondering if there is a better method.

How is this usually handled ? Is there an IC suited for this task ?

Thanks in advance !


[edited by: nneu at 7:27 PM (GMT 0) on 24 Jul 2019]