I am using EVAL-AD1938 for evaluating AD1938.
I am configuring AD1938 as a slave for both BCK and LRC. i.e. BCK and LRC will be provided by Master(FPGA in my case).
I am not able to find sink/source current information related to AD1938(and CPLD on board) which is required for me as I have to convert 1.8V to 3.3V (FPGA is working at 1.8V whereas CODEC can work at 3.3V only)
Request to help me for above requested information.