I am using EVAL-AD1938 for evaluating AD1938.
I am configuring AD1938 as a slave for both BCK and LRC. i.e. BCK and LRC will be provided by Master(FPGA in my case).
I am not able to find sink/source current information related to AD1938(and CPLD on board) which is required for me as I have to convert 1.8V to 3.3V (FPGA is working at 1.8V whereas CODEC can work at 3.3V only)
Request to help me for above requested information.
Unfortunately I do not have this information easily at my disposal. This part was designed a while back so it will take significant effort to open up the design files to extract this information. The CPLD is not our part so I do not have the information for that part.
You will be using a level translator. I would suggest you do not use one that automatically senses direction because they do not have very good drive strength and you will need good drive strength to run the signals to another PCB. I have made this mistake in the past so I always use level translators that you have to select the direction with a logic pin. If you also include provisions for damping resistors then you should not have any signal integrity issues as long as you use wires as short as possible and you are not trying to run at high sample rates or TDM 16.