I need your help to get some additional information while using AD1938.
If AD1938 is configured in master mode, will it continuously generate LRC and BCK even if all channels of ADC & DAC are muted?
Also, can someone please help me understand the rationale on why BCK and LRC clocks are free-running? Which operating scenario will demand BCK and LRC clocks to remain free-running?
Appreciate for your help and attention on this support request.
Yes, the LR clock and Bit clock will continue to run. They are simply divided down from the internal master clock rate. Just because you are muted the part internally is still being clocked and so the LRCLK and BCLK continue to have output.
The muting function is an audio function where the audio data goes to zero. It has nothing to do with the clocking section of the part.
There are many systems that operate using TDM8 with a sampling rate of 48kHz. This produces a bit clock rate of 12.288MHz which is exactly the desired frequency of the master clock in many systems. So the bit clock is used to drive the system master clock. So you would not want this to go away when the audio is muted.
In other systems the serial port output may go to a class-D amplifier with an I2S input. These parts often have a sleep mode that is entered when the bit clock goes away. There is a short startup time once it returns. It has to lock to the signal again. So if the bit clock never goes away you do not have that start up time when you want to un-mute.
If you need to stop the clocks then simply write to the register and place the serial port in slave mode and the clocks will stop.
Thank you for your attention.
Well, the MCU host which is being interfaced with AD1938 does not generate free running BCK and LRC even after MCU host I2S is enabled.
The MCU host I2S starts generating free running BCK and LRC only after at least one word(32bits) is written to its Tx FIFO.Once at least one word is written, the host I2S starts generating free-running BCK and LRC even if its internal Tx FIFO is not written with a new data.
This is the reason, I am trying to understand if such behavior from MCU host I2S is acceptable or not?
If not, under which end application scenario it will be a problem?
Once again, thank you for your attention and guidance.
I hope I am understanding your concerns properly.
If the AD1938 is the master for the entire system, if the ADCs and the DACs are masters then there should not be a problem unless your MCU host has a problem with the BCLK and LRCLK always on.
The AD1938 codec is not an MCU so the clocking is simple and there are no buffers, except the serial to parallel shift register. So once the PLL is setup and running the simple dividers will divide down that clock and send it out. It has nothing to do with the data. You MCU has the ability to make decisions which the codec does not have.
So if you have the MCU be the master then you may run into some problems. If there are no clocks at startup then the ADC is not an issue, the data will just be overwritten with new data until you start reading it out. Actually, as I think about it the ADC will simply stop converting if there are no clocks.
For the DAC it will stay stuck on one value. It will be zero at startup and you can mute it as well. Then once the clocks start it will start putting out analog signals. Then if the clocks stop the DAC will stop in its tracks. It will hold on the last value it received which means it will put out a DC level. Then when the audio starts back there may be a pop or click. If your MCU can guarantee to put out a zero before stopping the clocks then that will help. There may still be a slight DC offset but it should not be a problem and you should mute the DAC before stopping the clocks anyway.
So both of these cases is if the codec is setup as a slave for the clocks.
I must say that the Master Clock input should start shortly after power up and should not go away ever. The PLL locks to this signal so you do not want it to lock then unlock or lock to some noise signal when the master clock is stopped. So do not stop the MCLK input.
Thank you for your response.
The MCU that is hosting AD1938 will be master.
The point to note is, MCU does not generate BCK/LRC even if MCU has initialized I2S module.
The MCU starts generating clock as soon as FIRST time I2S buffer register is written with some value(i.e. desired or dummy). After this, MCU continues to generate BCK/LRC and does not stop it until I2S module is disabled.
I think this shall not be an issue as far as CODEC interface is concerned - please correct me if my understanding is not same as yours.
This should not be a problem. I am expecting that the master clock is there from power up and that the part is initialized and the PLL is locked. If there is no bit clock or LRCLK going to the serial ports then no data will be going in or out so it is really not a problem. It would be a good idea when the codec is initialized that the DACs are muted until the MCU starts generating the clocks.
What is happening with the Master Clock input to the PLL in the codec?
What frequency is the master clock and where is the clock coming from?
Will you be operating in Standalone mode or will you setup the codec with the MCU?