ADAU1966A PLL Locking Issue

Hi Dave,

We are using  ADAU1966A  in system design with direct master clock mode ,

MCLK : 3 MHz (768 X Fs )

sampling rate FS : 3.91 KHz

DBCLK & DLRCLK are measured at the IC pin. The following values are ,

DBCLK : 137.1389 KHz

DLRCLK : 4.28855 KHz

while reading register 0x01, the value is 2A instead of 2E.

I found that Internal PLL is not locked.and I am using loop filter as per  recommended for MCLKI in datasheet.

What can be the issue for PLL not locking?

Thanks in Advance



Changed the subject after splitting this off from another discussion.
[edited by: DaveThib at 8:32 PM (GMT 0) on 5 Feb 2019]
Parents
  • 0
    •  Analog Employees 
    on Feb 5, 2019 8:57 PM

    Hello Selvikavi,

    There are a few inconsistencies in your post that I need to clarify.

    First to answer your question about the PLL:

    There are many reasons as to why it will not lock.

    1)   Bad signal integrity on the master clock signal so it misses edges and or gets extra clock cycles. So the PLL will see that as the frequency changing too quickly to lock to.

    2) Bad power on the PLL VDD pin.

    3) Incorrect components used in the PLL Loop filter.

    4) PCB layout problems.

    5) Lots of noise on the ground and or power planes.

    6) Frequencies out of specifications.  This is your issue. The minimum frequency that the PLL can lock to is 6.9MHz. (Table 7 in the datasheet).

    So you need to be running in Direct clocking mode and so you need to disable the PLL.

    So you need to power down the PLL in Control Register 0

    Then in Control Register 1 you need to set bit 0  to a "1".

    Then the relationship between the master clock and the sampling rate needs to be exactly 512 x fs. I do not know how you are obtaining your frequencies or which is important, the master clock or the sampling rate. Either way, it needs to be 512 x fs.

    The Bit Clock and the LRCLK numbers you stated means that you have 32 bitclocks per sample period. So from this I assume you are running using two channels with 16 bit audio. There is no room for more bits than that.

    This info should get you started on the right track, we can work out some of the other details later.

    Dave T

Reply
  • 0
    •  Analog Employees 
    on Feb 5, 2019 8:57 PM

    Hello Selvikavi,

    There are a few inconsistencies in your post that I need to clarify.

    First to answer your question about the PLL:

    There are many reasons as to why it will not lock.

    1)   Bad signal integrity on the master clock signal so it misses edges and or gets extra clock cycles. So the PLL will see that as the frequency changing too quickly to lock to.

    2) Bad power on the PLL VDD pin.

    3) Incorrect components used in the PLL Loop filter.

    4) PCB layout problems.

    5) Lots of noise on the ground and or power planes.

    6) Frequencies out of specifications.  This is your issue. The minimum frequency that the PLL can lock to is 6.9MHz. (Table 7 in the datasheet).

    So you need to be running in Direct clocking mode and so you need to disable the PLL.

    So you need to power down the PLL in Control Register 0

    Then in Control Register 1 you need to set bit 0  to a "1".

    Then the relationship between the master clock and the sampling rate needs to be exactly 512 x fs. I do not know how you are obtaining your frequencies or which is important, the master clock or the sampling rate. Either way, it needs to be 512 x fs.

    The Bit Clock and the LRCLK numbers you stated means that you have 32 bitclocks per sample period. So from this I assume you are running using two channels with 16 bit audio. There is no room for more bits than that.

    This info should get you started on the right track, we can work out some of the other details later.

    Dave T

Children
No Data