We are using ADAU7002 to covert from PDM to TDM input. The condition is as below.
Our configuration is as below, and the TDM LRCK/BCK from host is 48k/12.288MHz TDM mode.
But we found the PDM_CLK output from ADAU7002 is 1.5MHz only, it should be 3.072MHz, is that right?
Also with the 1.5MHz clock, the DMIC have data output to ADAU7002, but we can't find the TDM_Data from ADAU7002?
Do you have any suggestion about this? Is the TDM format issue which cause the PDM clock frequency not correct?
Update some test waveform
Below is TDM input LRCK (48kHz)/ BCLK(12.288MHz), but no TDM data output
Below is PDM clock output from ADAU7002 (Blue line)
I'm also struggling with such a problem.
I suspected that this is a problem of fan -out of the driver (I'm using SPORT output from the SC589 as a source for the LRCLK). I tried to use a clock buffer on a different card and it wordek properly. I'm not sure, howevever if there is another reason, as I cannot refabricate the solution.
I'd appreciate if you caould share your findings.
Hello Allen and Tomtim,
The operation of this part is really quite simple. It will take the incoming LRCLK and generate a PDM clock of 64 x the LRCLK. So if you are getting an output of ~1.5MHz then pulses are being missed or there are a lot of reflections causing problems.
Then the 7002 looks at the ratio of the LRCLK and the BCLK to determine if the signal is an I2S signal or a PDM signal. You MUST have 32 bitclocks per audio channel. So if it is getting 64 BCLK periods per LRCLK period then the part will know it is stereo I2S. If it detects 128 BCLKs per LRCLK then it will know it is TDM 4 data.
The configuration pin will tell the 7002 how many 32 bit data fields to count before putting out the data.
So if the config pin is OPEN, then it will wait for slots 3 and 4 by not sending out anything during the first 64 bit clocks and then start sending out data on BCLK 65 to 128.
So if you are sending it a LRCLK of 48kHz and a Bit Clock of 3.072MHZ, (64 x) then you are sending it I2S format signal. Then if the Config pin is setup with the 47K pull up that I see in your schematic, then it is expecting a TDM 8 signal and will be waiting for slots 7 & 8 which will never happen and so no data is sent.
It will be counting for slots 1 - 6 to pass but after two slots the LRCLK pulse comes in for a new frame so the counting will start all over again. So you get no output.
So if you want TDM 8 output and on slots 7&8. Then you must send it a BCLK = 12.288MHz and set the config pull up to IOVDD with a 47K resistor.
Now Allen, I see in your post with the screenshots that you say you have a BCLK of 12.288MHz and you do not see anything on SDATA. If you have a 47k pull up then the data will be at the end of the frame and not the beginning. The last 12 bits will also be tristated because the 7002 will only drive the first 20 bits of the slot. So your screenshot looks normal, no data at that time.
Signal Integrity will be important.
Hi, Tomtim and Dave,
Sorry for late response.
We found the issue coming from the host BCK LRCLK format doesn't match the ADAU7002.
The LRCK rising edge should be sync with BCK falling edge, which is different from our host sending.
We modify the polarity of BCK in our host controller and the ADAU7002 can send the 3.072MHz PDM clock and also can send data to our host.
The datasheet Table7 LRCK setup/hold time should be I2S, not TDM due to the waveform show both the rising and falling.
Do you have any information about the TDM input requirement about the ADAU7002? We can do further verification.