ADAU7002 PDM output clock issue


We are using ADAU7002 to covert from PDM to TDM input. The condition is as below.

Our configuration is as below, and the TDM LRCK/BCK from host is 48k/12.288MHz TDM mode.

But we found the PDM_CLK output from ADAU7002 is 1.5MHz only, it should be 3.072MHz, is that right?

Also with the 1.5MHz clock, the DMIC have data output to ADAU7002, but we can't find the TDM_Data from ADAU7002?

Do you have any suggestion about this? Is the TDM format issue which cause the PDM clock frequency not correct?