From ADAU1777 information I understood that the group delay from ADC to DAC < 30usec , in 192Khz
Is there group delay information from DAC to ADC , in 192Khz ?
Is there group delay information from ADC to DAC , in 192Khz ?
Is there a max sample frequency limit?
The group delay specifications are from Analog->ADC->DSP->DAC->Analog.
Going through in a different order will not change the numbers. The only little snag is that if you truly are using the serial port to get to the DAC then analog back into the ADC then you will add the delay of the serial port and the ASRC. Those are also in the datasheet.
For the ADAU1401,
I do not see any group delay information in the datasheet so I would have to take some measurements. Is this information still needed? I know it has been a while since you posted this question. I am working on older unanswered questions.
The max sampling frequency will be governed by the max master clock frequency. In the 256x fs mode, the max master clock frequency will be a period of 73ns which is ~13,698,630 Hz. With this master clock rate the internal core clock will be ~54,794,520 Hz. This will be the number of instructions per second. Since running at the 192kHz setting you will have 256 instructions per sample period, dividing this by 256 will give you the max sampling rate. This comes out to be 214 kHz fs. Keep in mind that this would be running on the edge and that the master clock will have a variance so it is probably not a good idea to push it too far beyond the 192kHz fs.