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ADAU1978 TDM problem

Hello,

my ADC sends wrong datas on TDM, this is an example :

The BCLK and LRCLK signals are sent by a FPGA, they don't seem too bad (probed with a 2GHz active probe) :

LRCLK is sampled by the ADC on rising edge, here are the ADC registers :

 ADC 1 Read conf
 ADC1 - Reg@00 = 01
 ADC1 - Reg@00 = 01
 ADC1 - Reg@00 = 01
 ADC1 - Reg@00 = 01
 ADC1 - Reg@00 = 01
 ADC1 - Reg@01 = C1 -> MCLK used for PLL input
 ADC1 - Reg@02 = 4A
 ADC1 - Reg@03 = 7D
 ADC1 - Reg@04 = 3F -> LR_POL = 0 BCLK_EDGE = 0
 ADC1 - Reg@05 = 63 -> TDM16, Left Justified
 ADC1 - Reg@06 = 08 -> 32 BCLK per TDM slot, 24-bit, LRCLK/BCLK slave, 32BCLK/channel, MSB first, LRCLK is a single BCLK cycle wide pulse
 ADC1 - Reg@07 = 10
 ADC1 - Reg@08 = 32
 ADC1 - Reg@09 = F0
 ADC1 - Reg@0A = A0
 ADC1 - Reg@0B = A0
 ADC1 - Reg@0C = A0
 ADC1 - Reg@0D = A0
 ADC1 - Reg@0E = 02
 ADC1 - Reg@0F = FF
 ADC1 - Reg@10 = 0F
 ADC1 - Reg@11 = 00
 ADC1 - Reg@12 = 00
 ADC1 - Reg@13 = 00
 ADC1 - Reg@14 = 00
 ADC1 - Reg@15 = 20
 ADC1 - Reg@16 = 00
 ADC1 - Reg@17 = 00
 ADC1 - Reg@18 = 27
 ADC1 - Reg@19 = 00
 ADC1 - Reg@1A = 00
 ADC1 - Reg@1B = F8
 ADC1 - Reg@1C = 81
 ADC1 - Reg@1D = 00
 ADC1 - Reg@1E = 00
 ADC1 - Reg@1F = 00

+ one observation : when adding a small capacitor/or a probe on LRCLK, the ADC works normally

Any idea ?

Thanks,

Jérôme