ADAU1372 anti-aliasing filter at 16 kHz sample rate

Hi,

I am using a ADAU1372 codec at a sample frequency of 16 kHz and from measurements I found that a frequency of 8.1 kHz at the ADC input appears only 6 dB lower at 7.9 kHz at the ADC output (when compared to signals < 8 kHz) and that a signal of 7.9 kHz at the DAC input appears as two signals at the DAC output at 7.9 kHz and 8.1 kHz only 6 dB lower.

I would expect that an digital anti-aliasing filter was in place of at least - let's say 40 dB, but obviously that is not the case.

I am doing something wrong? Is there a setting to enable a digital anti-aliasing filter for a 16 kHz sample frequency?

If no, then does Analog Devices have a codec with similar requirements (sound quality, latency, power consumption) but with an anti-aliasing filter for a sample frequency of 16 kHz (possible alternatives: 24 kHz or 32 kHz)?

I can work around the problem by using the sample frequency of 48 kHz (or higher), which has a good anti-aliasing filter according to the specifications, and implementing my own sample rate converter with digital filter, but I prefer to have this done by the codec.

Kind regards,

Ad van de Voort

Videtur BV

Parents Reply
  • Hello Dave,

    Thanks for the fast response and sorry for my late reply (I was expecting an e-mail, but I found out that my e-mail notifications were turned off).

    We are using the EVAL-ADAU1372Z evaluation board, which has a 12.88 MHz crystal and that is what we use for the masterclock. The PLL is disabled. We are using ADC2 and ADC3 because of the stereo connector J22 on the board. The sampling rate for ADC2 and ADC3 is 192 kHz.

    I have included a file with the settings that might be important:

    Adau1372_settings.txt
        /**
         *  ADC, DAC MPPINS
         */
    
        // enable main clock:
        // bit 7: PLL_EN        : 0 disable PLL
        // bit 6: RESERVED      : 0
        // bit 5: SPK_FLT_DIS   : 0 enable I2C spike filter
        // bit 4: XTAL_DIS      : 0 enable crystal oscillator
        // bit 3: CLKSRC        : 0 external pin drives main clock
        // bit 2: RESERVED      : 0
        // bit 1: CC_MDIV       : 1 divide external clock by 1
        // bit 0: MCLK_EN       : 1 enable main clock
        drv_dsp_i2c0_reg_write_wadr(CLK_CONTROL, 0x03);
    
        // registers PLL_CTRL0 to PLL_CTRL6 are a "don't care"
    
        // register CLKOUT_SEL is a "don't care"
        // register REGULATOR: keep reset defaults
    
        // SOUT_SOURCE_0_1: use defaults
        // bits [7:4]: SOUT_SOURCE1: 0101 (0x5) Output ARSCR Channel 1
        // bits [3:0]: SOUT_SOURCE0: 0100 (0x4) Output ARSCR Channel 0
    
        // registers SOUT_SOURCE_2_3, SOUT_SOURCE_4_5, SOUT_SOURCE_6_7 are
        // a "don't care"
        // register ADC_SDATA_CH: keep reset defaults
    
        // registers ADC0_VOLUME, ADC1_VOLUME, ADC2_VOLUME, ADC3_VOLUME: keep
        // reset defaults
        // registers PGA_CONTROL_0, PGA_CONTROL_1: keep reset defaults
    
        
        /**
         *  General settings
         */
    
        // SAI_0: set data format and sample rate
        // bits [7:6]: SDATA_FMT    : 00 set to I2S
        // bits [5:4]: SAI          : 00 set to stereo I2S
        // bits [3:0]: SER_PORT_FS  : serial port sampling rate: 16 kHz
        drv_dsp_i2c0_reg_write_wadr(SAI_0, 0x03);
    
        // SAI_1: set ADAU as I2S master, other bits: keep defaults
        // bit 7: TDM_TS        : 0 (dc, keep defaults)
        // bit 6: BCLK_TDMC     : 0 (dc, keep defaults)
        // bit 5: LR_MODE       : 0 LRCLK mode: 50 % duty cycle
        // bit 4: LR_POL        : 0 I2S default
        // bit 3: SAI_MSB       : 0 MSB first
        // bit 2: BCLKRATE      : 0 32 BCLK cycles/channel
        // bit 1: BCLKEDGE      : 0 data changes on falling edge
        // bit 0: SAI_MS        : 1 ADAU is master for LRCLK/BCLK
        drv_dsp_i2c0_reg_write_wadr(SAI_1, 0x01);
    
        // register SOUT_CONTROL0 is only for TDM mode
        
    
        /**
         *  ADC settings
         */
    
        // DECIM_PWR_MODES: power on decimator and ADCs
        // bit 7: DEC_3_EN      : 1 enable ASRC3 decimator
        // bit 6: DEC_2_EN      : 1 enable ASRC2 decimator
        // bit 5: DEC_1_EN      : 0 disable ASRC1 decimator
        // bit 4: DEC_0_EN      : 0 disable ASRC0 decimator
        // bit 3: SYNC_3_EN     : 1 enable ADC3 filter
        // bit 2: SYNC_2_EN     : 1 enable ADC2 filter
        // bit 1: SYNC_1_EN     : 0 disable ADC1 filter
        // bit 0: SYNC_0_EN     : 0 disable ADC0 filter
        // Seems like a bug in ADAU1372: experiments have shown that enabling
        // only ADC2, ADC3, ASRC2 and ASRC3 with 0xCC is not enough and
        // ADC0, ADC1, ASRC0 and ASRC1 also need to be enabled (0xFF), even though
        // they are not used
        drv_dsp_i2c0_reg_write_wadr(DECIM_PWR_MODES, 0xFF);
    
        // register ADC_CONTROL0: ADC0 and ADC1: set to defaults
        drv_dsp_i2c0_reg_write_wadr(ADC_CONTROL0, 0x19);
    
        // ADC_CONTROL1: unmute ADC2 and ADC3
        // bits [7:6]: RESERVED     : 00
        // bit 5: RESERVED          : 0
        // bit 4: ADC3_MUTE         : 0 unmute ADC3
        // bit 3: ADC2_MUTE         : 0 unmute ADC2
        // bit 2: RESERVED          : 0
        // bits [1:0]: ADC_2_3_FS   : 01 ADC sample rate 192 kHz
        drv_dsp_i2c0_reg_write_wadr(ADC_CONTROL1, 0x01);
    
        // register ADC_CONTROL2: ADC0 and ADC1: set to defaults
        drv_dsp_i2c0_reg_write_wadr(ADC_CONTROL2, 0x00);
    
        // ADC_CONTROL3: enable ADC2 and ADC3
        // bit 7:      RESERVED     : 0
        // bits [6:5]: HP_2_3_EN    : 11 high pass filter at 8 Hz
        // bit 4:      DMIC_POL     : 0 (dc, keep defaults)
        // bit 3:      DMIC_SWAP    : 0 (dc, keep defaults)
        // bit 2:      DCM_2_3      : 0 source set to ADC
        // bit 1:      ADC_3_EN     : 1 enable ADC 3 (also set SYNC_3_EN bit and
        //                            DECIM_PWR_MODES)
        // bit 0:      ADC_2_EN     : 1 enable ADC 2 (also set SYNC_2_EN bit and
        //                            DECIM_PWR_MODES)
        drv_dsp_i2c0_reg_write_wadr(ADC_CONTROL3, 0x63);
    
        // ASRC_MODE: select channels 0 and 1
        // bits [7:4]: RESERVED     : 0
        // bits [3:2]: ASRC_IN_CH   : 00 Serial Input Port Channel 0 / 1
        // bit 1:      ASRC_OUT_EN  : 1 enable output ASRCs
        // bit 0:      ASRC_INT_EN  : 1 enable input ASRCs
        drv_dsp_i2c0_reg_write_wadr(ASRC_MODE, 0x03);
    
        // register ASRCO_SOURCE_0_1: make switch from ADC2 and ADC3 to
        // Output ASRC 0 and Output ASRC1
        // bits [7:4]: ASRC_OUT_SOURCE1 : 0111 (0x7) ADC3
        // bits [3:0]: ASRC_OUT_SOURCE0 : 0110 (0x6) ADC2
        drv_dsp_i2c0_reg_write_wadr(ASRCO_SOURCE_0_1, 0x76);
    
        // register ASRCO_SOURCE_2_3: keep reset defaults
    
        // registers ADC2_VOLUME, ADC3_VOLUME: reset to defaults
        drv_dsp_i2c0_reg_write_wadr(ADC2_VOLUME, 0x00);
        drv_dsp_i2c0_reg_write_wadr(ADC3_VOLUME, 0x00);
    
    
        /**
         *  DAC settings
         */
    
        // INTERP_PWR_MODES: enable ASRC and DAC power
        // bits [7:4]: RESERVED     : 0000
        // bit 3: MOD_1_EN          : 1 power up DAC Modulator 1
        // bit 2: MOD_0_EN          : 1 power up DAC Modulator 0
        // bit 1: INT_1_EN          : 1 power up ASRC 1 interpolator
        // bit 0: INT_0_EN          : 1 power up ASRC 0 interpolator
        drv_dsp_i2c0_reg_write_wadr(INTERP_PWR_MODES, 0x0F);
    
        // ASRC_MODE: input ASRCs already enabled at the ADC section
    
        // DAC_SOURCE_0_1
        // bits [7:4]: DAC_SOURCE1: 1101 (0xD) Input ASRC channel 1
        // bits [3:0]: DAC_SOURCE0: 1100 (0xC) Input ASRC channel 0
        drv_dsp_i2c0_reg_write_wadr(DAC_SOURCE_0_1, 0xDC);
    
        // OP_STAGES_MUTE: make sure headphone outputs are muted
        // bits [7:4]: RESERVED : 0000
        // bit [3:2]: HP_MUTE_R : 11 mute both right output pins
        // bit [1:0]: HP_MUTE_L : 11 mute both left output pins
        drv_dsp_i2c0_reg_write_wadr(OP_STAGE_MUTES, 0x0F);
    
        // DAC_CONTROL1: enable and mute DAC0 and DAC1
        // bits [7:6]: RESERVED : 00
        // bit 5: DAC_POL       : 0 normal input polarity (not inverted)
        // bit 4: DAC1_MUTE     : 1 mute DAC1
        // bit 3: DAC0_MUTE     : 1 mute DAC0
        // bit 2: RESERVED      : 0
        // bit 1: DAC1_EN       : 1 enable DAC1
        // bit 0: DAC0_EN       : 1 enable DAC0
        drv_dsp_i2c0_reg_write_wadr(DAC_CONTROL1, 0x1B);
    
        // registers DAC0_VOLUME, DAC1_VOLUME: reset to defaults
        drv_dsp_i2c0_reg_write_wadr(DAC0_VOLUME, 0x00);
        drv_dsp_i2c0_reg_write_wadr(DAC1_VOLUME, 0x00);
    
        // OP_STAGE_CTRL: power up headphone output
        // bits [7:6]: RESERVED : 00
        // bit 5: HP_EN_R       : 1 set right output in headphone mode
        // bit 4: HP_EN_L       : 1 set left output in headphone mode
        // bits [3:2]: HP_DN_R  : 10 HPOUTRN disabled, HPOUTRP enabled
        // bits [1:0]: HP_DN_L  : 10 HPOUTLN disabled, HPOUTLP enabled
        drv_dsp_i2c0_reg_write_wadr(OP_STAGE_CTRL, 0x3A);
        

    Kind regards,

    Ad

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