Facing a trouble to use SPI mode. To solve the problem could you please answer to following questions?
Q1. Does communication speed need to be lower than 400kHz to move to SPI mode after Power up? Q2. At what timing does communication speed need to be changed to use SPI mode in MHz order? Is immediately after pulling CLATCH_B low three times right timing?Q3. In case that I2C start condition (a high-to-low transition on SDA/COUT while SCL/CCLK remains high) is satisfied accidentally after Power Up, is it impossible to move to SPI mode?
Thank you for your support.
I'm working with Katsu.
I confirmed user system and detail waveform.
In D/S, needs CLATCH 3 times Low.
But, user system needs onec additional Low pulse.
They repeats until correct data read back.
In this case, CLATCH without pull down.
also, CLATCH with pull down.
User system is no problem.
First Low pulse is FPGA configuration time. this pulse is user design Issues.
So, remaining twice dummy reads.
Is there a limitation of Low pulse?
/ pulse width
I can't understand why needs additional pulse.
Please advise for our customer.
Thank you for the great scope plots. It is very helpful.
The CLATCH need to be low for 5ns before the first CCLK rising. You will have to adjust the scope to look closely at the fall time of the CLATCH in relation to the CCLK. What I notice on your SPI implementation is that the clock is always present. Normally we see no clock until it is time to transmit data. I do not know if this is part of the problem, it should not be a problem because clocks can always be present when communicating to another part but it is something I noticed that is different from what I usually see.
So I think this is a fall time issue with why it is different when you have a pull down resistor verses no pull down.
The only other important thing with the timing of the CLATCH is that it remains low for at least 10ns from when the last clock pulse goes low to high. This would only affect the data properly latching in and not the three dummy writes to put it into SPI mode.
Thank you for your quick responce and great support.
At the other test condition, The CCLK is only during CLATCH Low.
In this case, ADAU1361 is normal operation in 3 times CLATCH low.
It's just as you say.
They want to know the reason for unexpected trouble..
This is closely scope. I think SPI mode 3.
In this case, the first edge is falling.
So, it can't remains CCLK low.
And, First CLATCH low with pull down resister is looks like no clock.
is it problem?
In this case, user system is nomal operation by 3 times CLATCH low.
So,I think that CCLK is not necessary for put in SPI mode.
Can you point out the problem in this informations?
If you need, I can confirm the additional information for your support.