Facing a trouble to use SPI mode. To solve the problem could you please answer to following questions?
Q1. Does communication speed need to be lower than 400kHz to move to SPI mode after Power up? Q2. At what timing does communication speed need to be changed to use SPI mode in MHz order? Is immediately after pulling CLATCH_B low three times right timing?Q3. In case that I2C start condition (a high-to-low transition on SDA/COUT while SCL/CCLK remains high) is satisfied accidentally after Power Up, is it impossible to move to SPI mode?
Thanks for the very good testing you have done.
So am I to assume these boards are exactly the same boards? Are there any differences on the board?
So with that assumption I can say that something is different so lets investigate further.
Can you do a scope capture of the waveforms using a good oscilloscope's analog input (not digital input ports). It would also be good to use low capacitance FET probes if possible. Measure as close to the 1361 as you can.
Compare the good and the bad running at the same frequency. 1.152MHz or above.
I suspect you may find there are reflections or other signal integrity issues. Post the scope plots if you can.
Assuming you see a difference in the waveforms, Then the question is why?
Is there a part stuffed on one board but not the other?
Is another part which has connections to the SPI lines powered down?
Is a part missing and so therefore the termination is not there causing a reflection?
Is a wrong value of resistor or cap stuffed on one board and not the other?
Let me know what you find.
This part has been out for a while and I don't remember anyone having issues in the past. I will ask some of the other Apps engineers if they remember an issue.