ADAU1361 Trouble to use SPI mode

Hello,

Facing a trouble to use SPI mode. To solve the problem could you please answer to following questions?

Q1. Does communication speed need to be lower than 400kHz to move to SPI mode after Power up?
Q2. At what timing does communication speed need to be changed to use SPI mode in MHz order? Is immediately after pulling CLATCH_B low three times right timing?
Q3. In case that I2C start condition (a high-to-low transition on SDA/COUT while SCL/CCLK remains high) is satisfied accidentally after Power Up, is it impossible to move to SPI mode?

Best Regards,

    •  Analog Employees 
    on Apr 1, 2016 2:42 AM over 4 years ago

    Hello Katsu,

    Q1: No, it can be at the max SPI speed.

    Q2: You can use full speed SPI "immediately" after pulling the CLATCH line low three times. Now there will be a small delay for the internal multiplexers to switch over. I do not think that was characterized so I do not have that data. In looking at the other setup times I would expect this to be around 50ns or close to that. So I would wait a short time if possible before going forward with full speed communication.

    Q3: No, the CLATCH pin is always active and waiting for three transitions. These transitions can come at any time during operation and even at a really low  frequency. So this is why this pin needs to be pulled up if I2C is being used. The communications hardware is different for the I2C and the SPI so the state of the I2C state machine does not matter for the SPI engine. Once it is switched over to SPI mode the I2C section is no longer active.

    Dave T

    •  Analog Employees 
    on Apr 1, 2016 2:43 AM over 4 years ago

    Hello Katsu,

    I forgot to ask you a question!  What is the nature of the SPI problems you are having? What frequency are you operating?

    What are your symptoms?

    Dave T

  • Hello Dave,

    Thanks a lot for detailed answers.

    The SPI problem is that:
    One board (Board A) which is operating with CCLK=200kHz in SPI mode, this works normally.
    Another board (Board B) which is operating with CCLK=1.152MHz in SPI mode, it is not successful to communicate with SPI mode and IC looks frozen.

    Increasing CCLK of Board A to 2.4MHz: No problem.
    Decreasing CCLK of Board B to 288kHz: No problem

    Doing trouble-shooting now thus asked these questions here.

    Best Regards,
    katsu

    •  Analog Employees 
    on Apr 1, 2016 5:53 PM over 4 years ago

    Hello Katsu,

    Thanks for the very good testing you have done.

    So am I to assume these boards are exactly the same boards? Are there any differences on the board?

    So with that assumption I can say that something is different so lets investigate further.

    Can you do a scope capture of the waveforms using a good oscilloscope's analog input (not digital input ports). It would also be good to use low capacitance FET probes if possible. Measure as close to the 1361 as you can.

    Compare the good and the bad running at the same frequency. 1.152MHz or above.

    I suspect you may find there are reflections or other signal integrity issues. Post the scope plots if you can.

    Assuming you see a difference in the waveforms, Then the question is why?

    Is there a part stuffed on one board but not the other?

    Is another part which has connections to the SPI lines powered down?

    Is a part missing and so therefore the termination is not there causing a reflection?

    Is a wrong value of resistor or cap stuffed on one board and not the other?

    Let me know what you find.

    This part has been out for a while and I don't remember anyone having issues in the past. I will ask some of the other Apps engineers if they remember an issue.

    Dave T

  • Hello Dave,

    Thanks a lot for good suggestions. I passed the investigation to my colleague. I will share some more detail later but give me a while for summarizing.

    Best Regards,
    katsu