This post is to show what a good screenshot of I2S signals will look like on a scope and how your own screenshots should look when you send them over to us. Then we can get the most information out of them.
Regarding your scope setup there are a few little things that will help. When simply looking to see if the format is correct and the data is in the right place it is good to be able to see all the bits. Including the zeros. The best way to do that is to turn on the persistence in your scope and do not use the single sweep feature. When you use the single sweep you only capture one frame of data and it can be almost any number in the data stream and most likely you will not see where the MSB bit is exactly as it relates to the Bit Clock. So with persistence it will show many frames of data and with 2's compliment the MSB will be high for negative numbers so it is very easy to see where the bits start and stop. So let me start with a full frame:
In this screenshot you can see at least one entire frame. What I mean by a frame is one sample period which in this case is the LRCLK (Left Right Clock) shown in Yellow on channel 1.
It is important to trigger off of this LRCLK signal. At the bottom of the screen you can see that I was running at 48kHz for this example. If you have a scope that reads out frequency it is great to put it on the screen as well. I also have the bit clock frequency measured which is 64x fs.
So in this screenshot you can see that both channels of data are there. They are both 24 bits. There is no significant over or under shoot. Not much noise on the lines. But it is difficult to see the bit clock relationship so on to the next screenshot:
In this Screenshot I stretched out the timebase so that I can easily see the relationship of the bitclock to both the LRCLK and the data. I see that the bitclock is falling to trigger the next bit to be shifted out. So on the falling edges you can see the data transitions. Note that I was using a 0dBFS signal but if you are using a lower level you will not see some of the transitions on the left because they are all zeros all the time. Except for negative numbers where they are all ones so there are no transitions.
I can see the data starts transmitting after one complete bitclock cycle so it is 1 BCLK delayed. This is the I2S standard.
On the receiving end the shift register will clock in the data on the rising edge of the bit clock where the data is stable.
Then one more screenshot is good to send. One that is sort of between these first two:
On this screenshot you can actually count the bits if you like and you can count the number of empty bits after the data is finished. This can provide information that is helpful sometimes.
So when we ask for scope captures of I2S signals you can try to capture some that look like these and send them over.
For TDM data it is similar. One screenshot of the entire frame, one of the transition at the start of the frame and one more zoomed out to show one or two channels.
have you got an example of stereo output of this adc?
I don't understand? This post is about data transfer, it could be from an ADC or from a DSP to a DAC of other devices. I think I used a DSP to obtain these screenshots so no ADC was involved.
What are you looking for? What kind of example? Audio or SigmaStudio schematic?