How do I configure the SRAM memory mode in ADuCM3029?

Hello,

Our project is running into issues of running out of DSRAM and we are hoping to change the internal SRAM configuration to increase the DRAM size. 

I found this FAQ article about the topic concerning both the ADuCM302x and the ADuCM4050 : 

https://ez.analog.com/analog-microcontrollers/ultra-low-power-microcontrollers/w/documents/2470/faq-how-do-i-configure-the-sram-memory-in-aducm302x-or-aducm4050

but in the article they give the example for the ADuCM4050 using the IAR embedded workbench and this was not helpful for us using the CCES IDE. 

I was able to find the .icf file and copy it to my project but the step where it states to configure IAR was not clear: "Copy this .icf linker file in to your project directory and configure IAR to pick up this local linker file (see snapshot below)"

When I go to the CCES settings I can't find anything similar and any attempts I have made were not successful.

Any help would be great thanks,

Aleks

  • +1
    •  Analog Employees 
    on Jul 6, 2021 9:01 AM

    Hi Aleks,

    In order to configure the SRAM look for the LD file, located on your project directory RTE/Device/ADuCM3029/ADuCM3029.ld

    You can configure the SRAM to mode 2 to have a 64kB DSRAM, just make sure to disable the cache for this mode.

    For more details about this please refer to it's Hardware reference manual>>SRAM Region

    Regards,

    Jeric

  • Hello Jeric,

    Thank you for your reply. While initially looking around I came upon this LD file when trying to configure the SRAM but did not see any blatant mode settings and on second inspection I still do not see how I would configure the SRAM to mode 2. In the ICF file there is a line in the code that explicitly shows this:


    // user-selectable SRAM mode
    // SRAM Banks 1 & 2 are dynamically configurable for hibernation retention at runtime
    // referred to here as "xRAM_bank#_retained_region", where x = i (instruction) or d (data) and # = 1 or 2
    define symbol USER_SRAM_MODE = 0;

    but when looking in the LD file the only thing I could think that would resemble this is near the beginning of the code talking about memory:

    /*
    * Portions Copyright (c) 2016 Analog Devices, Inc.
    *
    * Based on Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld file in
    * ARM.CMSIS.4.5.0.pack.
    */

    /* Linker script to configure memory regions. */
    MEMORY
    {
    /* The first 0x180 bytes of Flash bank0 */
    FLASH0 (rx) : ORIGIN = 0x00000000, LENGTH = 0x180
    /* The remaining bytes of Flash bank0 */
    FLASH (rx) : ORIGIN = 0x00000180, LENGTH = 256k - 0x180
    /* SRAM bank 0+1 */
    DSRAM_A (rwx) : ORIGIN = 0x20000000, LENGTH = 16k
    /* SRAM bank 3 */
    DSRAM_B (rwx) : ORIGIN = 0x20040000, LENGTH = 16k
    }

    /* Library configurations */
    GROUP(libgcc.a libc.a libm.a libnosys.a)

    /* Linker script to place sections and symbol values.
    * It references the following symbols, which must be defined in code:
    * Reset_Handler : Entry of reset handler
    *
    * It defines the following symbols, which code can use without definition:
    * __exidx_start
    * __exidx_end
    * __copy_table_start__
    * __copy_table_end__
    * __zero_table_start__
    * __zero_table_end__
    * __etext
    * __data_start__
    * __preinit_array_start
    * __preinit_array_end
    * __init_array_start
    * __init_array_end
    * __fini_array_start
    * __fini_array_end
    * __data_end__
    * __bss_start__
    * __bss_end__
    * __end__
    * end
    * __HeapLimit
    * __StackLimit
    * __StackTop
    * __stack
    * __Vectors_End
    * __Vectors_Size
    */
    ENTRY(Reset_Handler)

    SECTIONS
    {
    .vectors :
    {
    KEEP(*(.vectors))
    __Vectors_End = .;
    __Vectors_Size = __Vectors_End - __Vectors;
    __end__ = .;
    } > FLASH0

    .security_options :
    {
    . = ALIGN(4);
    KEEP(*(.security_options))
    . = ALIGN(4);
    } > FLASH

    .text :
    {
    *(.text*)

    KEEP(*(.init))
    KEEP(*(.fini))

    /* .ctors */
    *crtbegin.o(.ctors)
    *crtbegin?.o(.ctors)
    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
    *(SORT(.ctors.*))
    *(.ctors)

    /* .dtors */
    *crtbegin.o(.dtors)
    *crtbegin?.o(.dtors)
    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
    *(SORT(.dtors.*))
    *(.dtors)

    *(.rodata*)

    KEEP(*(.eh_frame*))
    } > FLASH

    .ARM.extab :
    {
    *(.ARM.extab* .gnu.linkonce.armextab.*)
    } > FLASH

    __exidx_start = .;
    .ARM.exidx :
    {
    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
    } > FLASH
    __exidx_end = .;

    /* To copy multiple ROM to RAM sections,
    * uncomment .copy.table section and,
    * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
    /*
    .copy.table :
    {
    . = ALIGN(4);
    __copy_table_start__ = .;
    LONG (__etext)
    LONG (__data_start__)
    LONG (__data_end__ - __data_start__)
    LONG (__etext2)
    LONG (__data2_start__)
    LONG (__data2_end__ - __data2_start__)
    __copy_table_end__ = .;
    } > FLASH
    */

    /* To clear multiple BSS sections,
    * uncomment .zero.table section and,
    * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
    /*
    .zero.table :
    {
    . = ALIGN(4);
    __zero_table_start__ = .;
    LONG (__bss_start__)
    LONG (__bss_end__ - __bss_start__)
    LONG (__bss2_start__)
    LONG (__bss2_end__ - __bss2_start__)
    __zero_table_end__ = .;
    } > FLASH
    */

    __etext = .;

    .data : AT (__etext)
    {
    __data_start__ = .;
    *(vtable)
    *(.data*)

    . = ALIGN(4);
    /* preinit data */
    PROVIDE_HIDDEN (__preinit_array_start = .);
    KEEP(*(.preinit_array))
    PROVIDE_HIDDEN (__preinit_array_end = .);

    . = ALIGN(4);
    /* init data */
    PROVIDE_HIDDEN (__init_array_start = .);
    KEEP(*(SORT(.init_array.*)))
    KEEP(*(.init_array))
    PROVIDE_HIDDEN (__init_array_end = .);


    . = ALIGN(4);
    /* finit data */
    PROVIDE_HIDDEN (__fini_array_start = .);
    KEEP(*(SORT(.fini_array.*)))
    KEEP(*(.fini_array))
    PROVIDE_HIDDEN (__fini_array_end = .);

    KEEP(*(.jcr*))
    . = ALIGN(4);
    /* All data end */
    __data_end__ = .;

    } > DSRAM_B

    .bss :
    {
    . = ALIGN(4);
    __bss_start__ = .;
    *(.bss*)
    *(COMMON)
    . = ALIGN(4);
    __bss_end__ = .;
    } > DSRAM_B

    .heap (COPY):
    {
    __HeapBase = .;
    __end__ = .;
    end = __end__;
    KEEP(*(.heap*))
    __HeapLimit = .;
    } > DSRAM_A

    /* .stack_dummy section doesn't contains any symbols. It is only
    * used for linker to calculate size of stack sections, and assign
    * values to stack symbols later */
    .stack_dummy (COPY):
    {
    KEEP(*(.stack*))
    } > DSRAM_A

    /* Set stack top to end of DSRAM_A, and move stack limit down by
    * size of stack_dummy section */
    __StackTop = ORIGIN(DSRAM_A) + LENGTH(DSRAM_A);
    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
    PROVIDE(__stack = __StackTop);

    /* Check if data + heap + stack exceeds DSRAM_A limit */
    ASSERT(__StackLimit >= __HeapLimit, "region DSRAM_A overflowed with stack")
    }

    But it only seems to refer to the Flash ROM and Data SRAM and not Instruction SRAM. When looking in the hardware reference for the ADuCM302x under the SRAM Configuration we find:

    Instruction SRAM vs Data SRAM


    If the PMG_TST_SRAM_CTL.INSTREN bit is asserted, 32 KB of SRAM is mapped at start address 0x1000_0000
    as Instruction SRAM. 32 KB of data SRAM is mapped in two sections, the first starting at 0x2000_0000 and second
    starting at 0x2004_0000. If cache memory feature is used, only 28 KB is available for instruction SRAM.

    If PMG_TST_SRAM_CTL.INSTREN bit is 0 and cache is disabled, the 64 KB of SRAM is mapped as data
    SRAM. The memory is arranged in two sections, the first one (32 KB) is mapped at start address 0x2000_0000 and
    the second one (32 KB) at 0x2004_0000. If cache memory feature is used, the second section will only map 28 KB,
    so the total data SRAM available is 60 KB.

    By default, at power up and hardware reset, the 32 KB of SRAM is made available as instruction SRAM. If the user
    needs to exercise the option of using a total of 64 KB data SRAM, the PMG_TST_SRAM_CTL.INSTREN bit
    must be programmed to zero at the start of the user code.

    For our purposes we wanted to use Mode 3 with the cache enabled, so would I need to change the Memory portion of the LD file to read as such:

    /* Linker script to configure memory regions. */
    MEMORY
    {
    /* The first 0x180 bytes of Flash bank0 */
    FLASH0 (rx) : ORIGIN = 0x00000000, LENGTH = 0x180
    /* The remaining bytes of Flash bank0 */
    FLASH (rx) : ORIGIN = 0x00000180, LENGTH = 256k - 0x180
    /* SRAM bank 0+1 */
    DSRAM_A (rwx) : ORIGIN = 0x20000000, LENGTH = 32k
    /* SRAM bank 3 */
    DSRAM_B (rwx) : ORIGIN = 0x20040000, LENGTH = 28k
    }

    I have already added #define ADI_DISABLE_INSTRUCTION_SRAM and #define ENABLE_CACHE to the startup_ADuCM3029.c file and #define ADI_DISABLE_INSTRUCTION_SRAM to the reset_ADuCM3029.s file to take care of the both enabling the Cache and disabling the ISRAM on startup and reset as per the link in my original post:

    In case selecting USER_SRAM_MODE 2 or 3 (ISRAM disabled), it is also required to use the #define ADI_DISABLE_INSTRUCTION_SRAM macro in the reset_ADuCMxxxx.s and startup_ADuCMxxxx.c files in your project. 

    In case selecting USER_SRAM_MODE 1 or 3 (Cache enabled), it is also required to use the #define ENABLE_CACHE macro in the startup_ADuCMxxxx.c file in your project. 

    I am not sure if this is the correct location since when looking to where these defines are located, the ENABLE_CACHE macro is located in the system_ADuCM3029.c file and ADI_DISABLE_INSTRUCTION_SRAM is only located in the reset file.

    I am just trying to make sure that I don't accidentally do something that will brick or break the Evaluation board we have.

    Thanks,

    Aleks

  • 0
    •  Analog Employees 
    on Jul 7, 2021 2:13 AM in reply to Aleks89

    Hi Aleks,

    On CCES you have to manually configure the SRAM to mode 2 please refer to it's Hardware reference manual Figure 1-2

    -Jeric