Known Issues for ADuCM350 Silicon and Support Material

ADuCM350 Known Silicon Issues


ADuCM350 V1.4 silicon will release in March 2016. The change from V1.2 to V1.4 is a minor metal edit to improve the robustness of the high frequency, internal RC oscillator (HFOSC). Both MAN_ID and CHIP_ID information will be updated as part of this change.

Issue Description Workaround(s)
VBACK domain leakage Excessive leakage on VBACK domain when in use as backup supply. No solution available. It is recommended not to use SuperCap/VBACK mode.
UPLL pre-charging requirement UPLL must ne pre-charged before being used. SDK Version 2.4+ includes extra lines of code when using the UPLL to pre-charge the VCO loop.
High frequency crystal (HFXTAL) and duty cycle correction (DCC) block It has been found that when the HFXTAL and DCC block are used as the root clock source, it is sensitive to digital noise. Always use the system PLL (SPLL) as the root clock when the HFXTAL is source.
System PLL and USB PLL (SPLL/UPLL) Status Bit The SPLL/UPLL status bit threshold is too low and can cause the SPLLUNLOCK / UPLLUNLOCK bit to set when it is locked. Use SPLL / UPLL lock bit(s) (SPLLLOCK / UPLLLOCK) to reliably determine when the PLL is locked initially. Do not use SPLLUNLOCK / UPLLUNLOCK bit as a reliable indicator that the PLL has lost lock.



ADuCM350 Datasheet

 

In Rev.A of the ADuCM350 datasheet, there is an error in Figure 31 and Figure 32. For both figures, the Z value is incorrect. It should read:

    Z = 140Ω + 68nF

Also, the Y-axis label should read:

    Number of Measurements

The same corrections apply to both Figure 31 and Figure 32. It should also be noted that the capacitors used for these measurements (including the accuracy measurements in Figures 29 and 30) were COG capacitors with 1% tolerance. This tolerance may cause a slight deviation from the ideal value.

 

 

I2C Block

 

Full I2C errata document available here.

Issue Description Workaround(s)
I2C bus hangs when configured as slave Tx During a read from the master to slave, if the slave’s FIFO is empty, the slave should NACK the master’s request. Then it should release the bus allowing the master to generate a STOP condition. In the case of the slave’s FIFO buffer being empty, if data is loaded when the ninth SCL clock is high, the slave generates an ACK to the master and the MSB of read data is sent on the following SCL positive edge. If the MSB is 0, the SDA line will be held low and the slave will wait for extra SCL clocks to transmit the remaining bits. When this happens, the I2C master detects a NACK and then generates a STOP condition. Master arbitration is lost due to the SDA line being indefinitely low.
  1. Placing valid data in the Slave Tx FIFO.
  2. Set the BUS_CLR_EN bit in the I2CMCON register. If this bit is set, the master will initiate a Bus-Clear operation by sending up to 9 extra SCL cycles.
  3. Set EARLYTXR bit in the I2CSCON register. Setting this bit enables a transmit request just after the positive edge on the SCL line during the read bit transmission.
  4. Resetting the slave interface by disabling/enabling the slave.
I2C master fails to operate when the sum of the values in HIGH and LOW in the I2CDIV register has a value of less than 18 (0x12)

In an attempt to minimize the power consumption of the I2C interface, it may be desirable to set the PCLK frequency to 1MHz and set the SCL frequency to 100kHz. Using the provided formula, this would lead to the following HIGH and LOW values in the I2CDIV register:

HIGH = (REQD_HIGH_TIME / PCLK_PERIOD) – 2

HIGH = ((10us / 2) / 1us) – 2

HIGH = 3

LOW = (REQD_LOW_TIME / PCLK_PERIOD) – 1

LOW = ((10us / 2) / 1us) – 1

LOW = 4

When these values are programmed, the I2C master will not function.
  1. Use the adi_I2C_SetMasterClock() function to set the SCL frequency. Ensure to check for a valid return code.
  2. Do not program values to the HIGH and LOW fields in the I2CDIV register which give a sum of less than 18 (0x12).
I2C slave hangs the I2C bus when clock stretching is enabled

Clock stretching is an I2C feature that allows a slave device to temporarily pause communication by holding SCL low (for example, a slave device receives a READ request from a Master but, its Transmit FIFO is empty).

Clock stretching is enabled setting the STRETCHSCL bit in the I2CSCON register to 1. If this is done on the rising edge of SCL a glitch can occur. Other devices might interpret this as a real clock pulse and it could cause the bus to hang.

 It is recommended that the clock stretching feature is not used.

 

 

Software Development kit.

Example

Version

Issue

Resolution
AFE_Examples SDK 2.3.0.0 The workspace file, AFE_Examples.eww is missing from the AFE_Examples folder. This workspace was intended to allow all of the AFE example projects to be opened in a single workspace. Each of the examples are still present and functional. The workspace file (AFE_Examples.eww) is attached to this document.

Current Profiling

SDK 2.2.0

Lack of Readme

Refer to AN-1282 Application Note in Documentation Folder.

Captouch_5ButtonsTest

SDK 2.2.0

“Right” and “Left” buttons do not work

These pads are used as external interrupts on board. Remove R63 and R65. See Eval-ADuCM350 motherboard schematic for details.

Captouch_5ButtonsTest

SDK 2.2.0

UART Comms Does not work

The simplest fix is to call “test_Init()” after “adi_initpinmux()” instead of before. Baud Rate is 9600.

gpio_test, GpioTest,ThreadSpi.

SDK 2.2.0

Lack of Readme

M5 needs to be connected for VDD_IO supply.

LK14 needs to be inserted for VLCD_VDD supply.

Reveiew Pin-Out for GPIO supplies

Mipi_SSD1963_Test

SDK 2.2.0

No Hardware

This display has been discontinued by supplier. Code is just for reference only.
AmperometricMeasurement SDK 2.2.0 No option to change the value of RCAL or RTIA in software. The functions to set the values of RCAL and RTIA are available in afe.c. See the Amperometric Measurement FAQ for instructions on how to use them and where to insert them. http://ez.analog.com/docs/DOC-11063
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