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Q:  What is the difference between SPI0/1 and SPIH?

A: Each SPI has identical functionality, though SPIH is capable of higher transfer rates. From an SPI programming and users model perspective, SPIH, SPI0, and SPI1 are identical. The main difference between SPIH and SPI0/SPI1 is the internal bus interface that they are connected to. SPIH is connected to a higher performance advanced peripheral bus (APB), which is always clocked at the higher system clock rate (HCLK) and contains fewer modules requiring arbitration. SPI0 and SPI1 are connected to the main advanced peripheral bus (APB), which selectively can be clocked at a lower rate (PCLK) and whose latency is more uncertain due to a greater number of modules requiring arbitration. This means that under higher data rates, SPIH can move data more efficiently and with lower latency. SPIH is recommended for use with high data rate peripherals.

Q: Are there any restrictions in programming the SPI in DMA mode?

A: All SPI DMA transfers are 16-bit wide and the DMA should be programmed accordingly. For example, if 16 bytes of data are to be transferred over the SPI, the DMA should be programmed to perform eight 16-bit transfers. If 17 bytes are to be transferred, eight 16-bit transfers would be required, the additional byte is discarded. Data errors will occur if the DMA transfers are programmed as byte-wide transfers. This improves DMA efficiency and reduces DMA interrupt overhead. Odd-sized data byte counts in DMA mode cause data buffer overruns.

Q: What is the functionality of TIM bit in the SPI_CONTROL register?

A: The TIM bit defines the mode of transfer initiation (in Master mode) and interrupt generation (in master/slave modes).

      a. It should be set for all cases involving a Tx (either Tx-only or full-duplex).

      b. For transfers involving Rx only, this bit should be cleared.

When TIM=1, SPI starts the transfers with a write to the SPI TX register.

When TIM=0, SPI expects a read of Rx-FIFO to start the dta transfer. And most importantly, this read should happen when a byte transmission is not going on. That is, when there is no SCLK toggling happening over the interface.

Q: I am using SPI1 to transfer data from the ADuCM350 on the Eval-ADUCM350EBZ. The SCLK doesn't look right and data will only transfer successfully at very low data rates. What is the cause of this? Is it an SPI drive strength problem?

A: This is not an SPI drive strength problem. The SPI1 SCLK pin can also be used as an external GPIO. For this reason, a push-button switch (S4) has been implemented on the Eval-ADUCM350EBZ motherboard. This button has an associated de-bounce capacitor (C5) and this cap is affecting the SLI1 SCLK. The solution is to remove 0r resistor R12 from Eval-ADUCM350EBZ, which will isolate the cap and switch.

Q: Is there a minimum high (inactive) time for CS between transfers?

A: Yes. If CS is to go high (inactive) between transfers, it should be high for a minimum of 1 SCLK period.