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ADuCM360 VDAC interpolation mode

We need to revise the datasheet to relax the INL spec for VDAC interpolation mode.(Relative accuracy).


Some background:

When interpolation mode is selected, the VDAC output is “dithered” between 2x codes.

An external filter is required to filter the output voltage to a steady DC voltage.

Interpolation mode improves resolution (DNL) but, it does not improve INL. So  If
the VDAC INL is +/-3LSBs for a part in normal 12-bit mode, then this will scale
to +/-12LSBs at 14-bit level and +/-48LSBs at 16-bit level.

Next steps:

We are going to revise the ADuCM360 datasheet to reflect the information above.

The current datasheet INL or Relative accuracy specification only holds true if closed loop control of the VDAC output is implemented - i.e., the output voltage is measured by the ADC.

Also, another requirement is to ensure that the interpolation mode clock is <=100KHz.

The reason for this is to ensure the VDAC output is settled - the settling time of the VDAC is 10uS.

So, if the interpolation mode clock is >=100KHz, the VDAC is dithering between 2x non-settled voltage levels.

This will result in degraded resolution (DNL <14-bits.).

To apply an interpolation clock of <100kHz to the VDAC, the system clock (UCLK) must be <=3.2MHz. This means an external clock source is required for UCLK.

ADI are planning on addressing this issue in the future.