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Cyclo-Voltammetry example project not giving expected results

Category: Hardware
Product Number: ADUCM355

Hello!

I'm trying to match the results of output of the ADuCM355- EVAL board, using the "M355_ECSns_CycloVoltammetry" example project, to that of a conventional potentiostat done over a 3 lead ECS in Ferro/Ferri Cyanide solution. I'm using a ramp voltage of -0.3-0.6 V, steps of 10 mV and scan rate of 100 mV/s. However, when trying to apply the same parameters to the example project it seemed to "trim" out a part of the complete graph. Achieving a somewhat similar graph structure is done by applying a greater voltage range (-1-1 V) and even then the graphs aren't identical and the max current significantly exceeds the one from the potentiostat.
I would appreciate assistance in the matter.

The desired output:

the received output for original parameters:

output for extended voltage range:

  

original parameters:

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  • After playing with the parameters I managed to reach the following graph:

    This was done by raising the voltage by a constant 0.32 V and reducing the current by a constant of 5 uA.

    Here are the new parameters:

    My questions are:

    1) why aren't my parameters in line with the alleged parameters? 

    2) What may cause the constant bias (both in voltage and current measures)?

    3) How can I overcome the gaps before the peaks, i.e force the current values to overlap at the ends of the voltage sweep? I assume they have something to do with some sort of selective bias, but I'm having trouble putting my finger on it...

    Thanks a lot!   

  • Hi,

    Could you please increase the sample delay and ramp duration and check:

    pRampCfg->RampDuration = 10*1000; /* Total duration of ramp signal. unit is ms. */
    pRampCfg->SampleDelay = 2.0f; /* Time between update DAC and ADC sample. Unit is ms. */

  • Thanks for your response!

    I've tried multiple combinations of the specified parameters, all of which affect the shape of the graph but still no luck with matching the alleged stacture.

    basically I calculated the average of the distance between the edges of the shape, and then subtracted it from the increasing part of the ramp and added it to the decreasing part of the ramp (so I can "sew" the edges together). by this I got the following:

    Meaning, I'm still getting the skew in the X-axis and still unable to explain the bias added/subtracted to the current respectively...

  • Hi,

    May I know if you have checked by varying pRampCfg->SampleDelay because enough time must be give for ADC to sample and convert the settled current input at each sampling instant.

  • Hi again!

    Thanks for your patience! Increasing the sample delay did the trick.

    this is the output for 50 ms delay:

    I would like to further ask though - 

    1) Is the current skew between the graphs also configurable or is it, by this point, a matter of statistical  bias?

    2) Is there a way to smooth the graph?

    thank you!

Reply
  • Hi again!

    Thanks for your patience! Increasing the sample delay did the trick.

    this is the output for 50 ms delay:

    I would like to further ask though - 

    1) Is the current skew between the graphs also configurable or is it, by this point, a matter of statistical  bias?

    2) Is there a way to smooth the graph?

    thank you!

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