Based on UG-1262 Rev A. page 14, the Digital Die can use the clock of AFE die. I am trying to use the 32MHz HFSOC of AFE die to further increase the processing speed. While trying to activate this feature, CLK CTL0[1:0] = 0x03, the MCU stops responding. Can you guide me on the proper sequence to enable this?
A couple of points to note:
- The digital die maximum clock rate is 26MHz. This is the max clock rate the memories and digital logic were tested and qualified to.
- Did you follow the steps in the user guide under the section "Connecting AFE Die clock to Digital die clock input"?
- Also note the clock ratio requirement between the AFE and digital die - see following from the user guide:
REQUIRED CLOCK RATIO BETWEEN DIGITAL DIE AND ANALOG DIE SYSTEM CLOCKSTo maintain reliable communications between the digital die and the analog die, the ratio of the digital die system clock frequency to the analog die system clock frequency must be within the range of 3:1 and 1:3. For example, if the digital die system clock is set to 6.5 MHz, the analog die system clock must be >2.2 MHz but <19 MHz. If this ratio is not maintained, the digital die can lose its communication link to the analog die.