we are working with aducm362. Our need is to do an oversampling by operating o sinc2 filter along with sinc4 filter. We have configured all the registers according the hardware reference manual and datasheet, but we are not getting the ready interrupt.What is the method to set the step detection threshold? How we can make it working ? is there any example codes available which will do over sampling ?
Sorry, no example code for this case.
The register for setting the step detection threshold is STEPTH register, there are total 1024 steps. To enable the step detection, please note the below information.
1. Configure DETCON register. Be sure to enable the SINC2 (bit), select the used ADC (bit), and correct RATE (bit[1:0]). An example of function is shown below.
2. Configure the STEPTH register to make sure the threshold.
3. Interrupt is recommended to use. The interrupt for step detection is sinc2 interrupt not ADC interrupt. The function of interrupt is shown below.
4. Be sure to enable ADC conversion.
When we use sinc3 filter of ADC1, The Sigma Delta modulator has frequency of 125KHz, the OSR is found out by OSR= Fs/Fn, where Fn = 2* Nyquist rate.i.e, 125KHz/Fn is our OSR. since the frequency of input signal will be always a constant value so the Fn also will be a constant value, then how can we vary OSR ? we can control the SF and AF, but with this we can alter only the decimation factor. How we can achieve a control over OSR ? Also the final data we get through ADC1DAT register and the conversion equation given is (Vref/2^28) * ADC1DAt and also it is given that we will get an output of 1.2V. in thgis register our data will be of 21 bits, if we substitute the maximum value of 21 bit it will gives an output of 19mv only. Please give a solution for how we can use the over sampling functionality of sinc3 filter and how we can take the correct data out?
Normally we say output rate when using sigma delta ADC with Sinc3 or Sinc4 filter. The SF and AF, decimation factor as you said, will control the output rate. The Fn, as my understanding, is the stop frequency of the measured signal. So the Fn is equal to the update rate. Then you can get the OSR.
There is a chapter talking about the ADC data register. Suppose the internal 1.2V reference is used, the calculation to the correct input signal value is 1.2*(ADC code/2^28). No matter how the pga gain is. For the noise performance, you can refer the table 2, 3, 4 and 5. The noise is different with different update rate and PGA gain value.
i am trying to do a over sampling of 100 using sicn3 (SF=10 AF=4), and when i read the value from adcxdat register, the data that i obtained is getting clipped and not in expected range. While reading the data do we need to include the sign bits and noise bits along with data or they can be masked ? Do you have any example code for over sampling using sinc3 filter ? how this SF and AF plays there role ? and can you explain how they work when we set for a particular value ? please provide a detailed explaination how a oversampling of 100 can be achieved ?
Not sure if you have ADuCM362 example codes. If not, please access the below web site to download the examples. You can find how to read and calculate a number as well as using sinc3 filter from the ADC example codes.
There is a tool called ADuCM362/ADuCM363 design filter response model.xlsx can help you to configure the update rate with different SF and AF values. You can find the tool on ADuCM362 product page.