I am using a ADuCM360 with:
ClkSel( CLK_CD6, // iSpiCd by 64 CLK_CD7, // iI2cCd CLK_CD0, // iUrtCd by 1CLK_CD7 // iPwmCd by 128 );
ClkCfg(CLK_CD0,CLK_HF,CLKSYSDIV_DIV2EN_DIS,CLK_UCLKCG); // Select CD0 for CPU clock ------- CLOCK intern
I use HFOCS 16Mhz
When I send some byte I can see the width of Stop bit is different from the others.
If I enable the clock divider. CLKSYSDIV = 1 then all bits have same width.
Does it happen to someone the same?
I use the samples codes
Sorry for replying the question late.
The case is strange based on your description. I haven't received this kind of feedback so far. How about other baud rate?
I would like to test this case on my test bench. However I am always on travel recently. So perhaps the test will happen in October.