ADC inputs on ADuC7060

Q 

Am analysing a 3rd-party design to try to understand behaviour and to assist in
rework. The design works very close to (& sometimes under) the 0.1V minimum
input for buffered ADC inputs. Can you please:
a) confirm that the VREF+/VREF- inputs are not buffered or subject to these
limits;
b) if I set ADC0CH[3:0] to  0011, can I measure this reference voltage? Do I
need to set ADC0REF[1:0] to 11 as well to ensure I measure it w.r.t. a separate
reference?
c) I have the block schematic of the ADC stage from the 'Engineering Zone'
discussions, but would like to understand in more detail exactly where the
input limits arise. Do you have a more detailed diagram - or ideally a spice
model - which could help explain? Is the limitation input or Op-Amp output
driving? What is the gain of the initial buffer stage, and are all the OpAmp
stages (including the differential output amp) subject to the limitations? One
of the measurement modes has a differential input close to the 0.1V limit with
little voltage between the inputs (is the minimum 0.5V VCM only to ensure that
the full range is available on the input, or does it imply an additional
limitation to ensure, for example, that an interim gain stage doesn't limit)?

 

A 

a) There are no buffers on the VREF+/- inputs. Therefore the input limits don’t
apply however, you should note the larger input current (>1uA) because there is
no input buffers.

b) Yes, it is valid to select the reference as the input channel to the ADC.
The input measured is the reference selected by ADC0REF bits, so the ADC should
report a result close to full-scale

c) We don’t have a Spice model – see appended picture from design spec for more
details.

Is the limitation input or Op-Amp output driving?
The limit is due the buffer connected to the output of the PGA not being fully
rail-to-rail

What is the gain of the initial buffer stage, and are all the OpAmp stages
(including the differential output amp) subject to the limitations?
In front of the PGA, there are pre-charge buffers that are unity gain. The only
gain applied is in stages 1 and 2 of the PGA. The buffer between the PGA and
modulator is also unity gain.

One of the measurement modes has a differential input close to the 0.1V limit
with little voltage between the inputs (is the minimum 0.5V VCM only to ensure
that the full range is available on the input, or does it imply an additional
limitation to ensure, for example, that an interim gain stage doesn't limit)?
Yes, the Vcm should be configured to ensure the gain stages of the PGA don’t
limit. If they set Vcm to 850mV or a similar value, they are assured the full
PGA output is valid.