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bug in ADUC7061, DAC error

I use DAC to output voltage, and use ADC1 to readback it from channel8.

Firstly, the data is wrong, so i checked leakage current, adc offset of ADC for several weeks.

Finally, I found the ADC is ok, but the DAC will not work correctly when P0.0~P0.3 are used as analogue input.

If P0  is configured as GPIO(include SPI/I2C), the DAC will work correctly.

But if P0 is configured as analogue input, and run from flash, DAC will not work correctly.

But, if the JLINK/ULINK is used to debug(in keil, by step by step, F10, or run mode, F5), DAC will work correctly.

But the device should run without JLINK at last, do you think so?

The proof is here.

I consider it as a bug, and i deem that this kind of bug can be modified by setting one or more registers in startup routin. But the registers are not open to user, so, factory should check this and give solution.