ADuC7024 PLL Lock

In the data sheet for the ADuC7024 it says the core stops executing when the PLL loses lock

"When the internal PLL loses lock, the clock source is removed by a gating circuit from the CPU, and the ARM7TDMI core stops executing code until the PLL regains lock. This feature ensures that no flash interface timings or ARM7TDMI timings are violated."

"In noisy environments, noise can couple to the external crystal pins, and PLL may lose lock momentarily. A PLL interrupt is provided in the interrupt controller. The core clock is immediately halted, and this interrupt is only serviced when the lock is restored."

Undocumented information on PLLSTA seems to suggest the opposite:

PLLSTA Bit 1 = LOCK

PLL lock status bit. This read-only bit when set indicates that the PLL loop is correctly tracking the crystal clock. If it is low it indicates that the PPL is not tracking the crystal clock. This maybe because the loop has not yet locked onto the crystal clock or it may be due to the absence of a crystal clock. In the latter case the PLL loop is placed in an open-loop condition with the VCO oscillating at its nominal frequency and providing system clocks.

Can someone clarify what actually happens when using an external crystal and the lock is lost? Thanks.