Permanently locked out from ADuC7024 after entering Nap Mode.

I've been testing switching from internal oscillator to external crystal using the procedure in the device data sheet (Rev C, page 55) and reproduced below. (This procedure was not in Rev A datasheet). This code is placed just after entering main() of the application

T2LD = 5;
TCON = 0x480;
while ((T2VAL == t2val_old) || (T2VAL > 3)) //ensures timer value loaded
IRQEN = 0x10; //enable T2 interrupt (commented out this line)
PLLKEY1 = 0xAA;
PLLCON = 0x01;
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON = 0x27; // Set Core into Nap mode
POWKEY2 = 0xF4;

I commented out the IRQEN line (to try something out) and built and ran the application. Since this time I have not been able to access the ADuC to re-program it. I am using IAR EWARM and a miDAS J-Link. I get error dialogue messages along the lines of "Unable to halt the ARM core".

I have tried holding the !RST pin low while powering up and then accessing using JTAG and other conditions, but I seem to be permanently locked out of the device. By holding !RST low while powering up I expected the ADuC7024 would not execute (the above) code to enter nap mode and that I could then use the JTAG connection to reprogram with a program that does enable the wakeup timer IRQ.

There is a related thread http://ez.analog.com/thread/3969 ("When debugging the ADuC70xx parts via JTAG, I sometimes encounter problems where the JTAG interface no longer works?"). I am not able to use ARMWSD to try a mass erase as the application has SIN and SOUT mapped to pins other than P1.0 and P1.1 and those pins have other uses.

Is there any way to recover? Also, why am I locked out, as I mentioned earlier I expect that if I hold the device in reset on power up it would not enter nap mode?

I could do with changing the bootloaded/kernel to map the UART to pins other than P1.0 & P1.1, but accoring to http://ez.analog.com/thread/3984?tstart=30 this is not possible.

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  • 0
    •  Analog Employees 
    on Sep 28, 2010 1:22 PM over 10 years ago

    Yes - the core need to be used for Flash erase/programming.
    The small code snippets are loaded via JTAG into SRAM and

    at the end a watch-/breakpoint is placed to communicate

    with the JTAG-state.machine. This is the standard for ARM-cores.

    More details to find in the ARM Technical Documentation.

    ARMWSD is written for up to 32 ports.

    Normally the port number can be changed back in

    Windows Device Manager for a number in this range - also if

    the ports are listed as used.

    The IRQ should execute as normal after wake-up from NAP - you may check this with a GPIO

    i.e. you can toggle a pin :

    if(IRQSTA & 0x00000010){
        GP0DAT ^= 0x00010000;            // Toggle P0.0 on IRQ entry
        T2CLRI = 0;
    }

Reply
  • 0
    •  Analog Employees 
    on Sep 28, 2010 1:22 PM over 10 years ago

    Yes - the core need to be used for Flash erase/programming.
    The small code snippets are loaded via JTAG into SRAM and

    at the end a watch-/breakpoint is placed to communicate

    with the JTAG-state.machine. This is the standard for ARM-cores.

    More details to find in the ARM Technical Documentation.

    ARMWSD is written for up to 32 ports.

    Normally the port number can be changed back in

    Windows Device Manager for a number in this range - also if

    the ports are listed as used.

    The IRQ should execute as normal after wake-up from NAP - you may check this with a GPIO

    i.e. you can toggle a pin :

    if(IRQSTA & 0x00000010){
        GP0DAT ^= 0x00010000;            // Toggle P0.0 on IRQ entry
        T2CLRI = 0;
    }

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