I've been testing switching from internal oscillator to external crystal using the procedure in the device data sheet (Rev C, page 55) and reproduced below. (This procedure was not in Rev A datasheet). This code is placed just after entering main() of the application
T2LD = 5;TCON = 0x480;while ((T2VAL == t2val_old) || (T2VAL > 3)) //ensures timer value loadedIRQEN = 0x10; //enable T2 interrupt (commented out this line)PLLKEY1 = 0xAA; PLLCON = 0x01; PLLKEY2 = 0x55; POWKEY1 = 0x01; POWCON = 0x27; // Set Core into Nap mode POWKEY2 = 0xF4;
I commented out the IRQEN line (to try something out) and built and ran the application. Since this time I have not been able to access the ADuC to re-program it. I am using IAR EWARM and a miDAS J-Link. I get error dialogue messages along the lines of "Unable to halt the ARM core".
I have tried holding the !RST pin low while powering up and then accessing using JTAG and other conditions, but I seem to be permanently locked out of the device. By holding !RST low while powering up I expected the ADuC7024 would not execute (the above) code to enter nap mode and that I could then use the JTAG connection to reprogram with a program that does enable the wakeup timer IRQ.
There is a related thread http://ez.analog.com/thread/3969 ("When debugging the ADuC70xx parts via JTAG, I sometimes encounter problems where the JTAG interface no longer works?"). I am not able to use ARMWSD to try a mass erase as the application has SIN and SOUT mapped to pins other than P1.0 and P1.1 and those pins have other uses.
Is there any way to recover? Also, why am I locked out, as I mentioned earlier I expect that if I hold the device in reset on power up it would not enter nap mode?
I could do with changing the bootloaded/kernel to map the UART to pins other than P1.0 & P1.1, but accoring to http://ez.analog.com/thread/3984?tstart=30 this is not possible.
the only way to recover the ADuC7024 is to do a mass-erase in that case.
You can do this as explained in the mentioned thread with ARMWSD.
Only from the default UART pins.
Or you need to implement any kind of SW in your application which can
do this mass-erase from within your application - i.e. via password protected
command over in your communication.
During RESET the part has no clock and so the access via JTAG is limited.
You can't download and execute code into SRAM - what is normally required
for FLASH-erase/programming via JTAG.
The only chance you possbly can try, but depends on how quick after release of
the RESET the NAP is executed, you can possibly get control via JTAG if you
start the download at the same time.
But the chance is very small.