How to connect JTAG pins in final PCB design?

are the JTAG input pins, [TDI, TMS, TCK] pull up resistors necessary for normal operation [not debugging] ?

designing a small board and removal of a few resistors would help layout and routing [using a ADuC7061...]

i would add the pull up resistors on to the JTAG cable.or separate board used when debugging.

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  • 0
    •  Analog Employees 
    on Oct 15, 2010 2:37 PM over 10 years ago

    The 13K recommendation in the latest datasheet as against 13K on the mini-kit board is to minimize power consumption due to this pull-up.

    13K is the maximum value to ensure a safe pull-up with minimum current consumption.

    Unused analog pins are safest connected to ground.

    Unused digital GPIO pins have an internal pull-up therefore these can be left unconnected.

    The JTAG pins should be tied to Vdd externally with pull-ups - see datasheet.

    Regarding flash endurance. The datasheet spec is  a min.10,000 erase/write cycles (1 cycle = 1 erase+1 write) under JEDEC Lifetime spec A117 conditions.

    This specification is very much temperature dependent - see figure 22 of the datasheet.

    If your system operates in ~ 25C constantly, then the number of read/write cycles is ~170,000

    Regarding the Timers:

    Firstly, the timers have 2 x standard modes of operation - free running and periodic.

    In Free running mode, the timers run constantly and the TxVAL value goes from zero to full scale, overflows and starts again.

    In periodic mode, the timer runs from zero (or full scale) to the value in TxLD. In this mode, the timer is reloaded always on when TxVAL reaches the value in  TxLD

Reply
  • 0
    •  Analog Employees 
    on Oct 15, 2010 2:37 PM over 10 years ago

    The 13K recommendation in the latest datasheet as against 13K on the mini-kit board is to minimize power consumption due to this pull-up.

    13K is the maximum value to ensure a safe pull-up with minimum current consumption.

    Unused analog pins are safest connected to ground.

    Unused digital GPIO pins have an internal pull-up therefore these can be left unconnected.

    The JTAG pins should be tied to Vdd externally with pull-ups - see datasheet.

    Regarding flash endurance. The datasheet spec is  a min.10,000 erase/write cycles (1 cycle = 1 erase+1 write) under JEDEC Lifetime spec A117 conditions.

    This specification is very much temperature dependent - see figure 22 of the datasheet.

    If your system operates in ~ 25C constantly, then the number of read/write cycles is ~170,000

    Regarding the Timers:

    Firstly, the timers have 2 x standard modes of operation - free running and periodic.

    In Free running mode, the timers run constantly and the TxVAL value goes from zero to full scale, overflows and starts again.

    In periodic mode, the timer runs from zero (or full scale) to the value in TxLD. In this mode, the timer is reloaded always on when TxVAL reaches the value in  TxLD

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