How to connect JTAG pins in final PCB design?

are the JTAG input pins, [TDI, TMS, TCK] pull up resistors necessary for normal operation [not debugging] ?

designing a small board and removal of a few resistors would help layout and routing [using a ADuC7061...]

i would add the pull up resistors on to the JTAG cable.or separate board used when debugging.

  • The pull-up resistors on the JTAG pins, TDI/TCK/TMS are required to ensure that no unexpected glitches occur on any of these lines that corrupt either the flash contents or the ARM7 cores operation.

    There are weak internal pull-ups present internally on each of these pins and these are enabled by default. In a non-noisy environment, these pull-ups may suffice but, for optimum safety, we always recommend the addition of external pull-ups as documented in the datasheet.

    What is most important is that the nTRST/BM pin is pulled high externally by a 13K resistor as mentioned in the datasheet - failure to add this may result in the part entering boot mode after every reset sequence.

  • hello Mike

    thanks

    but 13K not 10K? - see R14 in Eval-ADuC7061MK.pdf

    for an ADuC7061... chip

    how should the unused pins be terminated?

    especially VREF+ and VREF-

    and other input pins

    also what is the limit of rewrites to flash

    i would like to keep a running timer and record total time running in flash

    updating it every 1 minutes or so, does not have to be too accurate

    can you clear up info regarding timers

    especially

    timer0 - reloads value from T0LD when overflow occurs

    timer1 and 2 - reloads from T1LD/T2LD when overflow occurs or T1CLRI/T2CLRI is written to

    timer 3 not sure when T3LD is loaded

    regards

    enzo

  • The 13K recommendation in the latest datasheet as against 13K on the mini-kit board is to minimize power consumption due to this pull-up.

    13K is the maximum value to ensure a safe pull-up with minimum current consumption.

    Unused analog pins are safest connected to ground.

    Unused digital GPIO pins have an internal pull-up therefore these can be left unconnected.

    The JTAG pins should be tied to Vdd externally with pull-ups - see datasheet.

    Regarding flash endurance. The datasheet spec is  a min.10,000 erase/write cycles (1 cycle = 1 erase+1 write) under JEDEC Lifetime spec A117 conditions.

    This specification is very much temperature dependent - see figure 22 of the datasheet.

    If your system operates in ~ 25C constantly, then the number of read/write cycles is ~170,000

    Regarding the Timers:

    Firstly, the timers have 2 x standard modes of operation - free running and periodic.

    In Free running mode, the timers run constantly and the TxVAL value goes from zero to full scale, overflows and starts again.

    In periodic mode, the timer runs from zero (or full scale) to the value in TxLD. In this mode, the timer is reloaded always on when TxVAL reaches the value in  TxLD

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