In the guidelines for implementation high speed I2C (NXP) clock stretching after ACK is mandatory. If you operate in 100 kHz mode, things even get worse….
How is this defined for ADUC702x as it ignores the clock stretching completely? This means that under clock stretching condition SCL goes high long after SDA went high. Next thing produced is a repeated start condition.... Just rubbish to follow as each of the two I2C channels controls 2 TPVs.
Setup: ADUC7026 and TI's TPV5051am (sorry this was on customer's demand). I2C interrupt processing takes place in a 10µs timer ISR. The video decoder inserts up to 64us of clock stretching after ACK and this fully complies with the I2C spec.
Any ideas for a workaround - except bit-banged I2C on your side? I can provide logic analyzer plots on demand.
I promised to be back with the screenplots: how it should be and how it works with the ADUC7026. ' ADUC7026 and clock stretching.pdf ' is attached.
Have a great day.