We are using the ADUC7021 in a reference design. We are not planning on using pins 18 and 21. Do you see any issues tying these pins directly to VDD?
Tying P0.3 and P0.5 to VDD is fine.
Note, P0.3 is also the nTRST pin – don’t tie this to ground as you could encounter debug issues with the JTAG interface.
You should be aware that these pins contain weak internal pull-up resistors - ~100K to IOVDD.