ADuC7024 ADC - Misc questions

Hi,


I have a few questions regarding the behaviour of the ADC peripheral on the ADuC7024 that I hope can be commented on:


i) After an ADC conversion has completed (ADCReady = 1) are the contents of bits 0 to 15 in ADCDAT all 0 or other/undefined?


ii) Data sheet Rev C, P44 says that reading ADCDAT clears ADCReady (ADCSTA, Bit 0). Does this also clear the ADC Channel (bit 7) in IRQSIG?


iii) With ADCCON configured for conversion on Timer 1 (bits 2:0 = 001) is it acceptable to read ADCDAT after a previous conversion has been performed (ADCReady = 0) and while a new conversion is in progress (ADCBUSY = 1)? I want to avoid the possibility of reading a value that is neither the result of the previous, or current conversion, such as when the result is being transferred internally to ADCDAT?


iv) What happens if ADCCON is written to/changed, while an ADC conversion is in progress (ADCBusy = 1) - does it affect the conversion in progress?


v) What happens if ADC channel is changed (ADCCP) while an ADC conversion is in progress (ADCBusy = 1) - does it affect the conversion in progress?


Thanks.

Parents
  • In this last example of IRQ processing you say "the same bit in IRQSTA will stay set until the IRQSTA register is read" but previously said "it is latched into IRQSTA and the relevant bit in IRQSTA will not get cleared until the interrupt is fully serviced". These seem like different behaviour.

    I can't see how reading IRQSTA would clear any of its bits, as determining the source of the IRQ in the ISR, as below, involves reading IRQSTA and in that case after the first read then all other tests would fail.

    if ((IRQSTA & TIMER1_BIT) != 0)
    {
    }
    if ((IRQSTA & UART_BIT) != 0)
    {
    }
    if ((IRQSTA & ADC_BIT) != 0)
    {
    }

    :

    Could you clarify when and which bits will be cleared in IRQSTA on the ADuC7024?

    If all bits within IRQSTA are cleared automatically when returning from IRQ_Handler(), then if a conditional method were used to handle the IRQ sources, such that all are not neccesarily handled in a single pass through the ISR then there could be a difference in non-latching IRQSIG interrupt sources (like the external interrupt pin you use as an example) and peripherals interrupts that latch a bit in IRQSIG, so that only unhandled (latched) interrupt sources with a bit still '1' in IRQSIG will cause a retrigger of the corresponding bit in IRQSTA.

    I see that the interrupt system for the ADuC7023 and ADuC7034 must be different from the ADuC7024 as for these parts it says:

    "IRQSTA/FIQSTA should be saved immediately upon entering the interrupt service routine (ISR) to ensure that all valid interrupt sources are serviced."

    Which I presume must mean the ISR must be styled as:

    IRQSTA_COPY = IRQSTA;

    if ((IRQSTA_COPY & TIMER_BIT) != 0)
    {
    }
    if ((IRQSTA_COPY & UART_BIT) != 0)
    {
    }
    if ((IRQSTA_COPY & ADC_BIT) != 0)
    {
    }

    :

    The ADuC7023 also says "FIQSTA is a read-only register that provides the current enabled FIQ source status (effectively a logic AND of the FIQSIG and FIQEN bits)", while the ADuC7034 says "IRQSTA provides the status of the IRQ source that is currently enabled (that is, a logic AND of the IRQSIG and IRQEN bits)".

Reply
  • In this last example of IRQ processing you say "the same bit in IRQSTA will stay set until the IRQSTA register is read" but previously said "it is latched into IRQSTA and the relevant bit in IRQSTA will not get cleared until the interrupt is fully serviced". These seem like different behaviour.

    I can't see how reading IRQSTA would clear any of its bits, as determining the source of the IRQ in the ISR, as below, involves reading IRQSTA and in that case after the first read then all other tests would fail.

    if ((IRQSTA & TIMER1_BIT) != 0)
    {
    }
    if ((IRQSTA & UART_BIT) != 0)
    {
    }
    if ((IRQSTA & ADC_BIT) != 0)
    {
    }

    :

    Could you clarify when and which bits will be cleared in IRQSTA on the ADuC7024?

    If all bits within IRQSTA are cleared automatically when returning from IRQ_Handler(), then if a conditional method were used to handle the IRQ sources, such that all are not neccesarily handled in a single pass through the ISR then there could be a difference in non-latching IRQSIG interrupt sources (like the external interrupt pin you use as an example) and peripherals interrupts that latch a bit in IRQSIG, so that only unhandled (latched) interrupt sources with a bit still '1' in IRQSIG will cause a retrigger of the corresponding bit in IRQSTA.

    I see that the interrupt system for the ADuC7023 and ADuC7034 must be different from the ADuC7024 as for these parts it says:

    "IRQSTA/FIQSTA should be saved immediately upon entering the interrupt service routine (ISR) to ensure that all valid interrupt sources are serviced."

    Which I presume must mean the ISR must be styled as:

    IRQSTA_COPY = IRQSTA;

    if ((IRQSTA_COPY & TIMER_BIT) != 0)
    {
    }
    if ((IRQSTA_COPY & UART_BIT) != 0)
    {
    }
    if ((IRQSTA_COPY & ADC_BIT) != 0)
    {
    }

    :

    The ADuC7023 also says "FIQSTA is a read-only register that provides the current enabled FIQ source status (effectively a logic AND of the FIQSIG and FIQEN bits)", while the ADuC7034 says "IRQSTA provides the status of the IRQ source that is currently enabled (that is, a logic AND of the IRQSIG and IRQEN bits)".

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