ADuC7060/61: Extra 60uS settling time - please explain?

When the ADuC7060 ADCs are used with more than a single channel (e.g. the multiplexer setting is changed periodically) -- there is a delay of several samples before the output data is settled.

However, there is "An additional time of approximately 60 us per ADC is required before the first ADC is available" - comment for Table 46, page 48, datasheet Rev.C

What is this 60 us? Where is it coming from?

  • 0
    •  Analog Employees 
    on Nov 24, 2011 4:12 PM

    The extra 60uS at the end of a first sample on a new channel is additional time taken by the digital filter to complete its computation. It also includes computations based on gain and offset compensation calculations. Because some of the filter computations are shared between the 2 x ADCs, this delay can be up to 2x 60uS (120uS). This delay is only present for the first sample on selecting a new ADC input.

    It’s a digital computation based on the 512kHz clock. Therefore, worst case the drift due to temperature will be +/-3%. Supply voltage has no affect. Assuming both ADCs are constantly enabled, then the delay caused by the filter computation will be constant.

  • 0
    •  Analog Employees 
    on Apr 29, 2019 10:35 AM
    This question has been closed by the EZ team and is assumed answered.