ADuC7024 - SPICON bits clarification

I'm after clarification on the meaning of two bits in SPICON of the ADuC7024 as the data sheet (Rev D) is not clear.

Is there any plan to roll out an errata sheet or Rev E data sheet to correct all known errors and omissions? I was told that several known issues in Rev C would be corrected in Rev D, but they're still present.

"Bit 10 - Slave output enable - Set by user to enable the slave output enable. Cleared by user to disable slave output enable"

Should this read as "Set by user to enable the slave output enable. Cleared by user  to disable slave output enable" ? If so, presumably this bit would only be relevant when in slave mode (SPICON.1 = 0).

Is this equivalent to the SPIOEN bit of the ADuC7023 ?, which is described as :

"SPIOEN Slave MISO output enable bit.


This bit is set for MISO to operate as normal.
This bit is cleared to disable the output driver on the MISO pin. The MISO pin is open-drain when this bit is clear.
"

"Bit 9 - Slave select input enable - Set by user in master mode to enable the output. Cleared by user to disable master output"

There seems to be a contradiction here between the use of the terms slave and master. Is this bit used to disable the MOSI pin function in multi-master configuration? If so, why the reference to "slave select input enable"? There doesn't seem to be an equivalent bit on the ADuC7023.

TIA.

  • 0
    •  Analog Employees 
    on Jan 19, 2012 4:37 PM

    In the SPICON register:

    Bit 10 on the ADuC7024  is equivalent to bit 9 on the ADuC7023, and only applies to slave mode.

    It should read:

    Slave MISO output enable bit: This bit is set for MISO to operate as normal. This bit is cleared to disable the output driver on the MISO pin. The MISO pin is open-drain when this bit is clear.

    Bit 9 of SPICON on ADuC7024 is described incorrectly, it should read:

    Chip Select output enable bit: Set by user in master mode to enable the chip select output. Cleared by user to disable the chip select output.

    This function has been removed from the SPI control register in more recent designs such as ADuC7023 as it can be acheived by not selecting the chip select functionality in the serial port mux (SPM7 configured in mode 0 instead of mode 2).

  • Thanks for clearing that up.

    So to enable SPICSL function, does both SPICON[9] need setting AND SPM7 configured in mode 2, or would just either of these settings be sufficient?

    Similarly to disable SPICSL do I need SPICON[9] = 0 AND SPM7 = 0?

  • 0
    •  Analog Employees 
    on Jan 20, 2012 3:31 PM

    To enable SPICSL function SPICON[9] should be set and SPM7 configured in mode 2.

    To disable it, either SPICON [9] should be cleared or SPM7 configured in a mode other than mode 2.

  • 0
    •  Analog Employees 
    on Jan 25, 2012 3:22 PM

    Correction to my previous post:

    SPICON[9] = Chip Select output enable bit.

    Set by user in master mode to disable the chip select output.

    Cleared by user to enable the chip select output.

  • 0
    •  Analog Employees 
    on Feb 3, 2012 8:18 PM

    Note that configuring P1.7 as chip select in the serial port mux, when the SPI interface is configured in master mode with CS output enabled, disables/resets the SPI configuration.

    It is recommended to configure the serial port mux before the SPI interface.