How to clear PLL interrupt bit on ADuC702x?

What is the recommended way to clear the PLL (lock lost) interrupt bit on a ADuC702x?

On a related note, the data sheet says "In case of crystal loss, the watchdog timer should be used. During initialization, a test on the RSTSTA register can determine if the reset came from the watchdog timer.". Is there any way to tell if the watchdog timer reset was caused by a loss of external crystal as opposed to any other cause?

  • 0
    •  Analog Employees 
    on Mar 19, 2013 5:54 PM

    The PLL lock interrupt can be masked in the interrupt controller (IRQCLR/FIQCLR registers).

    There is no way to tell if the watchdog timer reset was caused by a loss of external crystal.

  • So the PLL lock interrupt flag can be masked but not cleared ?

  • 0
    •  Analog Employees 
    on Apr 29, 2013 5:48 PM

    It is possible to clear the PLL interrupt, but only if the PLL lock has been restored, by setting a bit in an undocumented register.

    This register PLLSTA is at address 0xFFFF0400.

    Writing a 1 to bit 0 clears the interrupts (if the PLL is locked).

  • Hi, Can you suggest a reliable procedure to force a loss of PLL lock for test purposes? The data sheet says "In noisy environments, noise can couple to the external crystal pins, and PLL may lose lock momentarily."

  • This information below was on the old Engineer Zone, but I don't know where it has gone


    MMA 607 posts since 07-Jul-2010

    PLL Lock ADuC702x 08-Jul-2010 12:03


    Sometimes in harsh environments the PLL Lock can be lost.

    A PLL Lock interrupt can be enabled on this event.

    But how can this interrupt be cleared?

    Is a SW-Reset the only way to recover from this ?


    Tags: clock, pll, lock, aduc702x

    MMA 607 posts since 07-Jul-2010


    Re: PLL Lock ADuC702x 08-Jul-2010 12:17

    This mainly happens in the cases where an external crystal is used.

    More robust is the internal oscillator.

    The best practice specifically in very noisy environments is of course issuing a SW-RESET and as extra protection of your system, for secure recovery from faulty conditions, the WatchDog should be activated.


    But the ADuC702x has a PLL status register (PLLSTA MMR), which is unfortunately not in the datasheet, but it is in the header-files i.e. coming with the Keil toolchain.

    If a PLL-Lock-Interrupt occurs and the PLL is not totally out of control you should be able to avoid a WD- or SW-RESET.

    To recover from such a event a IRQ- or FIQ-Handler can be implemented and the event can be cleared without going through a SW-Reset.


    Here below is the explanation of this PLLSTA MMR.

    PLLSTA 0xFFFF_0400


    Bit 0 = PLLI

    PLL interrupt bit. This bit is latched high if the LOCK signal from the PLL goes low. A write of one to this bit will clear it (assuming LOCK has returned) A zero has no effect.


    Bit 1 = LOCK

    PLL lock status bit. This read-only bit when set indicates that the PLL loop is correctly tracking the crystal clock. If it is low it indicates that the PPL is not tracking the crystal clock. This maybe because the loop has not yet locked onto the crystal clock or it may be due to the absence of a crystal clock. In the latter case the PLL loop is placed in an open-loop condition with the VCO oscillating at its nominal frequency and providing system clocks.


    Bit 2 = OSC_OK

    Oscillator okay. This is the clock detector output indicating the presence of a valid crystal clock.


    Bit 3 = VCO_OK

    When the VCO is powered, core clock is enabled after approx. 10uS to ensure the VCO frequency is stabilised. The status of the enable bit can be monitored via VCO_OK bit.

    EckartH 85 posts since 29-Jun-2010

    Re: PLL Lock ADuC702x 08-Jul-2010 12:3

    Simply write a 1 to the LSB of PLLSTA. e.g.

    PLLSTA = 1;

     This clears the PLLI PLL interrupt bit.

    In demanding conditions the PLLI bit is also very useful if a correct clock speed is required such as in UART communications. Clear the PLLI bit before communicating then check it after communicating. If PLLI is set the communication timing might have been wrong and corrective action should be taken. The same applies if accurate time needs to be generated or measured. Check the PLLI bit before and after the time critical section.