According to ADuC7026 datasheet,
nRS signal rising time is specified 0-4ns delay than ECLK rising time.
But the customer measured nRS rising time is about 5ns faster than external Xtal (40MHz) rising time.
I would like to know:
Each ECLK on timing specifications are based on ECLK pin out? (when using external Xtal like above 40MHz Xtal)
Thank you for your help in advance.
Can you clarify and detail your your question a bit more please?
Hello, Thank you for your response.
ECLK on Fig 13 on data sheet.
ECLK is appeared on Figure 13. External Memory Read on Data Sheet page 14.
Is this ECLK on Fig 13 same as ECLK output (E7 pin)?
In other word, does the customer can measure same as Fig. 13 signal timing with probing E7 pin ECLK output?
Thank you for your help.
If you mean either P0.7 on all ADuC702x in general and pin E7 on a ADuC7028, than this is correct, but must be configured that way as explained on page 58.
Thank you very much for your confirmation.
Yes, ECLK output (E7 pin) mean an appropriate configured MUXed pin as an ECLK.
So I understand that Fig 13 can be reproduce by user based on ECLK output port and others.